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Visitor elhsfu
Visitor
1,465 Views
Registered: ‎05-28-2018

PPLOC missing on UltraScale

When I try to route my design I got the following error:

 

INFO: [Route 35-16] Router Completed Successfully
ERROR: [Constraints 18-1026] HDPostRouteDRC-02: the boundary net clk_IBUF_BUFG connecting to the port x1_mul_clk_IBUF_BUFG of reconfigurable cell EDVO does not have PPLOC on it. The issue might be caused by un-routed boundary net. For detailed routing information, please use TCL command 'report_route_status'.
ERROR: [Constraints 18-1026] HDPostRouteDRC-02: the boundary net n_2_564_BUFG connecting to the port x1_mul_E[0] of reconfigurable cell EDVO does not have PPLOC on it. The issue might be caused by un-routed boundary net. For detailed routing information, please use TCL command 'report_route_status'.
ERROR: [Constraints 18-1026] HDPostRouteDRC-02: the boundary net n_3_722_BUFG connecting to the port x1_mul_exp_r_reg[0]_0[0] of reconfigurable cell EDVO does not have PPLOC on it. The issue might be caused by un-routed boundary net. For detailed routing information, please use TCL command 'report_route_status'.

 

 

But if you check the EDVO Cell pins it shows that the ports above contain partition pin locations.

 

If I run the report_route_status it says the design has no errors:

 

Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 37961 :
# of nets not needing routing.......... : 20388 :
# of internally routed nets........ : 17880 :
# of nets with no loads............ : 2508 :
# of routable nets..................... : 17573 :
# of fully routed nets............. : 17573 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

 

 

When I implement the same design on 7 series (xc7a200tfbg676-1) I don't have any problem.

 

Could you please check if there is any issue for UltraScale devices?

 

I am using 2018.2

 

I am attaching the placed DCP

 

Thanks

 

 

 

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12 Replies
Moderator
Moderator
1,409 Views
Registered: ‎11-04-2010

Re: PPLOC missing on UltraScale

Hi, @elhsfu ,

It seems that the rar file is corrupted.

Could you try to upload the opt.dcp?

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Visitor elhsfu
Visitor
1,398 Views
Registered: ‎05-28-2018

Re: PPLOC missing on UltraScale

Hi @hongh,

 

 

When I try to upload the DCP I got this message (even if I change the extension):

The attachment's edvo_base_place.dcp content type (application/octet-stream) does not match its file extension and has been removed.

 

Maybe it is an issue with Windows 10.

 

I am uploading the DCP in a zip file now (generated with 7-ZIP)

 

 

Thanks

 

 

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Moderator
Moderator
1,383 Views
Registered: ‎11-04-2010

Re: PPLOC missing on UltraScale

Hi, @elhsfu ,

You can try to modidy the clock root of the reported boudary clock signals:

Example tcl script:

open_checkpoint ./EDVO_BASE_PLACE.dcp
place_design -unplace
update_design -buffer_ports -cells [get_cells EDVO]

set_property USER_CLOCK_ROOT X2Y2 [get_nets -of [get_pins EDVO/x1_mul_E[0]]]

set_property USER_CLOCK_ROOT X2Y2 [get_nets -of [get_pins EDVO/x1_mul_exp_r_reg[0]_0[0]]]

set_property USER_CLOCK_ROOT X2Y2 [get_nets -of [get_pins EDVO/x1_mul_clk_IBUF_BUFG]]

place_design
route_design

 

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Visitor elhsfu
Visitor
1,369 Views
Registered: ‎05-28-2018

Re: PPLOC missing on UltraScale

Hi @hongh,

 

It didn't work.

Please see the log file.

Did you try it on your machine? If so, what version are you using?

 

 

Thanks

 

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Moderator
Moderator
1,308 Views
Registered: ‎11-04-2010

Re: PPLOC missing on UltraScale

Hi, @elhsfu , 

It looks to be the issue in 2018.2. The issue will be resolved in the next release of Vivado.

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Visitor elhsfu
Visitor
1,303 Views
Registered: ‎05-28-2018

Re: PPLOC missing on UltraScale

Ok. Fine.

I will give kudo and reply as accepted solution when I test the new release.

If there is a patch before the new release, it would be great to receive it.

Thanks

 

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Visitor elhsfu
Visitor
1,140 Views
Registered: ‎05-28-2018

Re: PPLOC missing on UltraScale

Hi @hongh,

I've just tried 2018.3 and it is still the same.

XLX was not able to solve it for this release?

Thanks

 

 

 

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Moderator
Moderator
1,121 Views
Registered: ‎11-04-2010

Re: PPLOC missing on UltraScale

Hi, @elhsfu ,

Actually the issue is resolved in 2019.1. 

In the current version, please try the below commands:

open_checkpoint ./EDVO_BASE_PLACE.dcp
place_design -unplace
update_design -buffer_ports -cells [get_cells EDVO]

reset_property HD.PARTPIN_RANGE [get_pins EDVO/x1_mul_exp_r_reg[0]_0[0] ]
reset_property HD.PARTPIN_RANGE [get_pins EDVO/x1_mul_E[0] ]
reset_property HD.PARTPIN_RANGE [get_pins EDVO/x1_mul_clk_IBUF_BUFG ]
set_property HD.PARTPIN_LOCS {RCLK_DSP_CLKBUF_L_X15Y209/CLK_HDISTR_R14 RCLK_DSP_CLKBUF_L_X15Y149/CLK_HDISTR_R14} [get_pins EDVO/x1_mul_exp_r_reg[0]_0[0]]
set_property HD.PARTPIN_LOCS {RCLK_DSP_CLKBUF_L_X15Y209/CLK_HDISTR_R8 RCLK_DSP_CLKBUF_L_X15Y149/CLK_HDISTR_R8} [get_pins EDVO/x1_mul_E[0]]
set_property HD.PARTPIN_LOCS {RCLK_DSP_CLKBUF_L_X15Y209/CLK_HDISTR_R2 RCLK_DSP_CLKBUF_L_X15Y149/CLK_HDISTR_R2} [get_pins EDVO/x1_mul_clk_IBUF_BUFG]
place_design
route_design

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Visitor elhsfu
Visitor
291 Views
Registered: ‎05-28-2018

Re: PPLOC missing on UltraScale

Hi,

It is very frustrating that 2019.1 did no solve this bug.

I am attaching my full script with the two files needed to run it.

Just unzip them in a folder and source EDVO_GNT_V05.tcl.

Could you please tell what should I do to make it run with Ultrascale devices? With 7 series it runs ok.

Thanks.

 

 

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Visitor elhsfu
Visitor
44 Views
Registered: ‎05-28-2018

Re: PPLOC missing on UltraScale

Hi,

 

Any update on thsi?

Thanks.


Edson

 

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Xilinx Employee
Xilinx Employee
29 Views
Registered: ‎05-03-2018

Re: PPLOC missing on UltraScale

Hi @elhsfu ,
Strange that 19.1 also did not give you good result. I will take a look at the issue and get back here asap. Thanks for your patience.
Gouttham

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Xilinx Employee
Xilinx Employee
24 Views
Registered: ‎05-03-2018

Re: PPLOC missing on UltraScale

Hi @elhsfu,
I have not run your script yet, but took a quick look. Can you try these suggestions, so that tool do not get confused and you follow the right methodology for the tool?
a) you are running place_design followed by place_design -unplace, iteratively with multiple ECOs in between. Can you please change your flow to do all necessary ECOs before opt_design, and do opt,place,route ?
b) Please pass HD.RECONFIGURABLE to any cell before opt_design is called.
c) For the firs pass, you need not manually set the PARTPIN_SPREADING. Allow tool to use the default values.
d) Clocks are being created after place_design in your flow,. This is not HD specific, but you should define all clocks ,ideally in the beginning of the design itself as XDC, worst case atleast before you do opt_design. Clock routing happens in placement itself.
Thanks,
Gouthan

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