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Explorer
Explorer
1,545 Views
Registered: ‎04-18-2017

PR: Issue with black box

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Hello,

 

I am following lab3 from https://www.xilinx.com/support/university/vivado/vivado-workshops/Vivado-partial-reconfiguration-flow-zynq.html to have 2 AxiLite reconfigurable modules via PCAP. I am trying to adapt the shipped example to my own design. They are two counters within a custom AxiLite IP. For the black box, I followed the example from UG901, Black Box section in VHDL. This is my design:

Screenshot from 2018-07-19 13-02-41.png

 

In AxiLitePR_Counter_v1_0_S00_AXI I instantiate the black box:

    inst_AxiLitePR: entity work.Counter PORT MAP(
        Clk => S_AXI_ACLK,
        Reset => S_AXI_ARESETN,
        Control => slv_reg1,
        Count => Result
    );

And "Counter" looks like this (foollowing UG901)

-- https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf (Page 160 - Black Box (VHDL) section.)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Counter is
    Port ( Clk : in STD_LOGIC;
           Reset: in STD_LOGIC;
           Control : in STD_LOGIC_VECTOR(31 downto 0);
           Count : out STD_LOGIC_VECTOR(31 downto 0));
end Counter;

architecture rtl of Counter is
    component Counter_black_box
        Port ( Clk : in STD_LOGIC;
               Reset: in STD_LOGIC;
               Control : in STD_LOGIC_VECTOR(31 downto 0);
               Count : out STD_LOGIC_VECTOR(31 downto 0));
   end component;
       
   attribute black_box : string;
   attribute black_box of Counter_black_box : component is "yes";
   
begin
    U1: Counter_black_box port map (Clk=>Clk, Reset=>Reset, Control=>Control, Count=>Count);
end rtl;

I synthesize this and after I open the static design's checkpoint I cannot see the instantiated design:

Screenshot from 2018-07-19 13-01-39.png

Therefore, there isn't a black box cell to continue with the partial reconfiguration flow.

 

I also tried to have the black box with just the entity:

-- https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf (Page 160 - Black Box (VHDL) section.)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Counter is
    Port ( Clk : in STD_LOGIC;
           Reset: in STD_LOGIC;
           Control : in STD_LOGIC_VECTOR(31 downto 0);
           Count : out STD_LOGIC_VECTOR(31 downto 0));
end Counter;

architecture rtl of Counter is

begin
end rtl;

But the result was the same.

 

Are those VHDL blocks correct? Is there any property that I should set before packaging the AxiIP?

Thanks for the help.

 

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Explorer
Explorer
1,596 Views
Registered: ‎04-18-2017

Re: PR: Issue with black box

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Hi @hongh,

 

Only having the entity like in my previous post it worked. I managed to reconfigure that black box.

View solution in original post

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Moderator
Moderator
1,485 Views
Registered: ‎11-04-2010

Re: PR: Issue with black box

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Hi, @aripod ,
Before you suspect the issue occurs during packaging the Axi_IP, you should synthesize the IP alone first and observe whether the black_box exists in the design already.
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Explorer
Explorer
1,458 Views
Registered: ‎04-18-2017

Re: PR: Issue with black box

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@hongh,

 

I synthesized the IP before packaging it and there is no black box there. So far I tried with the following 3 cases:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Counter is
    Port ( Clk : in STD_LOGIC;
           Reset: in STD_LOGIC;
           Control : in STD_LOGIC_VECTOR(31 downto 0);
           Count : out STD_LOGIC_VECTOR(31 downto 0));
end Counter;

architecture rtl of Counter is
begin
end rtl;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Counter is
    Port ( Clk : in STD_LOGIC;
           Reset: in STD_LOGIC;
           Control : in STD_LOGIC_VECTOR(31 downto 0);
           Count : out STD_LOGIC_VECTOR(31 downto 0));
end Counter;

architecture rtl of Counter is
    component CounterEmpty
        Port ( Clk : in STD_LOGIC;
               Reset: in STD_LOGIC;
               Control : in STD_LOGIC_VECTOR(31 downto 0);
               Count : out STD_LOGIC_VECTOR(31 downto 0));
       end component;
       
	attribute black_box : string;
   attribute black_box of CounterEmpty : component is "yes";

begin
end rtl;
-- This is exactly how it is shown on UG909 (black box in VHDL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Counter is Port ( Clk : in STD_LOGIC; Reset: in STD_LOGIC; Control : in STD_LOGIC_VECTOR(31 downto 0); Count : out STD_LOGIC_VECTOR(31 downto 0)); end Counter; architecture rtl of Counter is component CounterEmpty Port ( Clk : in STD_LOGIC; Reset: in STD_LOGIC; Control : in STD_LOGIC_VECTOR(31 downto 0); Count : out STD_LOGIC_VECTOR(31 downto 0)); end component; attribute black_box : string; attribute black_box of CounterEmpty : component is "yes"; begin U1: CounterEmpty port map(Clk => Clk, Reset => Reset, Control => Control, Count => Count); end rtl;

All 3 cases don't show a blackbox:

Screenshot from 2018-07-26 11-39-11.png

 

And as you can see, it is being instantiated properly:

Screenshot from 2018-07-26 11-41-27.png

How should I define it then?

 

Thanks for the help.

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Explorer
Explorer
1,447 Views
Registered: ‎04-18-2017

Re: PR: Issue with black box

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I now synthesized the black box like this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Counter is
    Port ( Clk : in STD_LOGIC;
           Reset: in STD_LOGIC;
           Control : in STD_LOGIC_VECTOR(31 downto 0);
           Count : out STD_LOGIC_VECTOR(31 downto 0));
end Counter;

And in the source's hierarchy:

Screenshot from 2018-07-26 14-18-11.png

 

Regardless, when I open the synthesized design, I get a critical warning (expected, I would say):

 [Project 1-486] Could not resolve non-primitive black box cell 'Counter' instantiated as 'AxiLitePR_Counter_v1_0_S00_AXI_inst/inst_counter' [/home/ariel/Documents/AxiLite/Vivado/AxiLitePR/ip_repo/AxiLitePR_Counter_1.0/hdl/AxiLitePR_Counter_v1_0_S00_AXI.vhd:388]

And the black box is there:

Screenshot from 2018-07-26 14-20-44.png

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Moderator
Moderator
1,436 Views
Registered: ‎11-04-2010

Re: PR: Issue with black box

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Hi, @aripod ,

In your design, Counter is a blackbox, but actually you are trying to create a black box "CounterEmpty" or "Counter_black_box ".

You can try to add the below content in AxiLitePR_Counter_v1_0_S00_AXI.vhd:

attribute black_box : string;
attribute black_box of Counter : component is "yes";

 

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Explorer
Explorer
1,597 Views
Registered: ‎04-18-2017

Re: PR: Issue with black box

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Hi @hongh,

 

Only having the entity like in my previous post it worked. I managed to reconfigure that black box.

View solution in original post

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Moderator
Moderator
1,420 Views
Registered: ‎11-04-2010

Re: PR: Issue with black box

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Hi, @aripod ,
Thank you for sharing the good news.
Please don't forget to close the thread.
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