10-31-2013 03:11 AM
I'm new in partial reconfiguration, I followed the ug702 guide, but unfortunately the example is written in verilog.
I'm searching for source codes written in VHDL. I found old one which uses a bus macro, I didn't understand what is a bus macro and if it is still used with new designs or they used it because the tools wasn't suuport the PR well.
10-31-2013 03:03 PM
I don't have a VHDL design example, although the tutorial design could probably be converted with fairly minimal effort.
Don't use any design that has bus macros. These were for a very old form of Partial Reconfiguration, and we replaced in the ISE tools with Proxy LUTs. If are you new to PR, I would also highly suggest you use Vivado. It is the same license currently, and this just went to production status in 2013.3. There are two documents on the Vivado Design flow:
This flow does require the Vivado 2013.3 tools.
I hope this helps.
11-07-2013 05:44 AM
11-20-2013 03:54 AM