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Adventurer
Adventurer
1,063 Views
Registered: ‎02-20-2017

PR placement failure for various logic cells

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I am working on a PR design on an XCKU035 with Vivado 2017.1. My goal is to make the entire device with the exception of the PCIe IP one big RM. I know I can do tandem configuration + FU, but normal configuration + PR offers advantages that I would like to take advantage of.

 

I am trying to build the first configuration. I have successfully syth'd the top level with a black box and the first RM OOC. Now trying to combine them to build the first full design, I am failing placement with the following error:

 

 

ERROR: [Place 30-642] Placement Validity Check : Failed to find legal placement.
Reason: Could not place shape in pblock userApp.
The unplaced cells are:
Cell userAppInst/HSD_BASE_APP_Inst/HSD_BD_inst/SYS_CLK_RESET/U0/EXT_LPF/POR_SRL_I of type SRL16E placed at site SLICE_X0Y0 (A6LUT)
Shape dimensions: Width = 1, Height = 1

userApp is the pblock containing the RM. userAppInst/HSD_BASE_APP_Inst/HSD_BD_inst/SYS_CLK_RESET is a "Processor System Reset" IP module. I tried manually placing this cell (at a random site) but placement then fails on another similar item. Any idea what is going on here? My pblock is defined as:

 

 

set userAppPblock [create_pblock -quiet userApp]
add_cells_to_pblock -quiet $userAppPblock [get_cells userAppInst]

resize_pblock $userAppPblock -add {SLICE_X91Y0:SLICE_X100Y299 SLICE_X86Y65:SLICE_X90Y299 SLICE_X0Y0:SLICE_X85Y299}
resize_pblock $userAppPblock -add {BITSLICE_CONTROL_X0Y0:BITSLICE_CONTROL_X1Y39}
resize_pblock $userAppPblock -add {BITSLICE_RX_TX_X0Y0:BITSLICE_RX_TX_X1Y259}
resize_pblock $userAppPblock -add {BITSLICE_TX_X0Y0:BITSLICE_TX_X1Y39}
resize_pblock $userAppPblock -add {DSP48E2_X0Y0:DSP48E2_X15Y119}
resize_pblock $userAppPblock -add {GTHE3_CHANNEL_X0Y8:GTHE3_CHANNEL_X0Y19}
resize_pblock $userAppPblock -add {GTHE3_COMMON_X0Y1:GTHE3_COMMON_X0Y4}
resize_pblock $userAppPblock -add {IOB_X1Y104:IOB_X1Y259 IOB_X1Y77:IOB_X1Y77 IOB_X1Y0:IOB_X1Y51 IOB_X0Y0:IOB_X0Y259}
resize_pblock $userAppPblock -add {MMCME3_ADV_X0Y0:MMCME3_ADV_X1Y4}
resize_pblock $userAppPblock -add {PCIE_3_1_X0Y1:PCIE_3_1_X0Y2}
resize_pblock $userAppPblock -add {PLLE3_ADV_X0Y0:PLLE3_ADV_X1Y9}
resize_pblock $userAppPblock -add {PLL_SELECT_SITE_X0Y0:PLL_SELECT_SITE_X1Y39}
resize_pblock $userAppPblock -add {RAMB18_X8Y26:RAMB18_X9Y119 RAMB18_X0Y0:RAMB18_X7Y119}
resize_pblock $userAppPblock -add {RAMB36_X8Y13:RAMB36_X9Y59 RAMB36_X0Y0:RAMB36_X7Y59}
resize_pblock $userAppPblock -add {RIU_OR_X0Y0:RIU_OR_X1Y19}
resize_pblock $userAppPblock -add {SYSMONE1_X0Y0:SYSMONE1_X0Y0}
resize_pblock $userAppPblock -add {XIPHY_FEEDTHROUGH_X0Y0:XIPHY_FEEDTHROUGH_X7Y4}

Thanks for any insight.

 

 

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1 Solution

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Adventurer
Adventurer
1,432 Views
Registered: ‎02-20-2017

Re: PR placement failure for various logic cells

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It seems like my definition of the update region pblock was problematic. I arrived at the previous definition by starting with and manipulating the update region pblock from the tandem ip example design. I re did it by just drawing the pblock in the vivado gui tool and this is what I am now using:

 

resize_pblock [get_pblocks userApp] -add {SLICE_X50Y65:SLICE_X99Y119 SLICE_X92Y0:SLICE_X99Y64 SLICE_X50Y60:SLICE_X86Y64 SLICE_X76Y0:SLICE_X81Y59}
resize_pblock [get_pblocks userApp] -add {DSP48E2_X14Y0:DSP48E2_X15Y47 DSP48E2_X8Y24:DSP48E2_X13Y47}
resize_pblock [get_pblocks userApp] -add {RAMB18_X6Y26:RAMB18_X9Y47 RAMB18_X6Y24:RAMB18_X8Y25}
resize_pblock [get_pblocks userApp] -add {RAMB36_X6Y13:RAMB36_X9Y23 RAMB36_X6Y12:RAMB36_X8Y12}
resize_pblock [get_pblocks userApp] -add {CLOCKREGION_X0Y2:CLOCKREGION_X3Y4 CLOCKREGION_X0Y1:CLOCKREGION_X1Y1 CLOCKREGION_X0Y0:CLOCKREGION_X2Y0}

The design now successfully implements.

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2 Replies
Adventurer
Adventurer
1,017 Views
Registered: ‎02-20-2017

Re: PR placement failure for various logic cells

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As an update, I tried manually placing that cell. I get the same error for two more cells (inside an AXI interconnect in a block design). I manually placed those too:

 

set_property LOC SLICE_X22Y20 [get_cells userAppInst/HSD_BASE_APP_Inst/HSD_BD_inst/SYS_CLK_RESET/U0/EXT_LPF/POR_SRL_I]
set_property LOC SLICE_X94Y34 [get_cells userAppInst/HSD_BASE_APP_Inst/HSD_BD_inst/axi_interconnect_0/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32]
set_property LOC SLICE_X94Y33 [get_cells userAppInst/HSD_BASE_APP_Inst/HSD_BD_inst/axi_interconnect_0/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32]

Now I get:

ERROR: [Place 30-99] Placer failed with error: 'Failed to move lutram to legal location'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

It gives me no details on what the specific failure is.

 

Any help would be appreciated. Thanks!

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Adventurer
Adventurer
1,433 Views
Registered: ‎02-20-2017

Re: PR placement failure for various logic cells

Jump to solution

It seems like my definition of the update region pblock was problematic. I arrived at the previous definition by starting with and manipulating the update region pblock from the tandem ip example design. I re did it by just drawing the pblock in the vivado gui tool and this is what I am now using:

 

resize_pblock [get_pblocks userApp] -add {SLICE_X50Y65:SLICE_X99Y119 SLICE_X92Y0:SLICE_X99Y64 SLICE_X50Y60:SLICE_X86Y64 SLICE_X76Y0:SLICE_X81Y59}
resize_pblock [get_pblocks userApp] -add {DSP48E2_X14Y0:DSP48E2_X15Y47 DSP48E2_X8Y24:DSP48E2_X13Y47}
resize_pblock [get_pblocks userApp] -add {RAMB18_X6Y26:RAMB18_X9Y47 RAMB18_X6Y24:RAMB18_X8Y25}
resize_pblock [get_pblocks userApp] -add {RAMB36_X6Y13:RAMB36_X9Y23 RAMB36_X6Y12:RAMB36_X8Y12}
resize_pblock [get_pblocks userApp] -add {CLOCKREGION_X0Y2:CLOCKREGION_X3Y4 CLOCKREGION_X0Y1:CLOCKREGION_X1Y1 CLOCKREGION_X0Y0:CLOCKREGION_X2Y0}

The design now successfully implements.

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