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siddadd
Observer
Observer
16,099 Views
Registered: ‎04-03-2012

Partial Reconfiguration - Failing in PAR

I am trying to use PR flow in Plan Ahead and it fails in PAR

The PAR report specifies the following problem:

--------------------------------------------------------------------+

Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
* TS_i_mmcm_fpga_top_clkout3 = PERIOD TIMEG | SETUP       |     0.188ns|     9.812ns|       0|           0
  RP "i_mmcm_fpga_top_clkout3"         TS_S | HOLD        |    -0.112ns|            |     116|        3753
  YS_CLK / 0.5 HIGH 50%                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_SYS_CLK = PERIOD TIMEGRP "TNM_SYS_CLK" | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0
   5 ns HIGH 50%                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_pcie_fifos_delay_path" TIG       | SETUP       |         N/A|     2.294ns|     N/A|           0
----------------------------------------------------------------------------------------------------------


When I go into the unrouted report, this is what I see:

 

   i_host_interface/dini_pcie/ep/pcie_clocking_i/clk_250
WARNING:ParHelpers:361 - There are 111 loadless signals in this design. This design will cause Bitgen to issue DRC
   warnings.

   clk200
   clk333
   clk400

I am not sure where the problem is. Any help will be appreciated.

0 Kudos
8 Replies
woodsd
Xilinx Employee
Xilinx Employee
16,091 Views
Registered: ‎04-16-2008

I don't see an errors in your post, so I'm not sure what you are concerned about. I'll try to address what I see here:

 

 - There was 1 constraint that was not applied.  This is probably related to the fact that there is a clock with no loads.

 - One constraint does not meet timing.  It looks like there is a small hold violation.  Examine this path in the detailed timing report to diagnose why this has occurred.

 - There are 111 loadless signals in the design.  This may not be an issue.  For many PR designs not all ports of an RP get used in every RM.  There may be ports that don't drive anything.  This would also occur in a black box RM.  

 

Do you get an error in PAR that the design is not fully routed, or just this warning?

0 Kudos
siddadd
Observer
Observer
16,089 Views
Registered: ‎04-03-2012

Hi woodsd,

 

Thanks for your reply.

 

Attached is a screenshot of my PlanAhead design run window. It errs out at 40% PAR.

 

Below is my PAR report which mentions 116 errors in Timing. I am not really sure whether Timing is the issue or the fact that some signals are not getting routed is hindering PAR to complete.

 

-------


WARNING:Par:288 - The signal clk333 has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal clk400 has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal clk200 has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_completion_info_selectram/Mram_mem4_RAMD_D1_O has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_completion_info_selectram/Mram_mem3_RAMD_D1_O has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_completion_info_selectram/Mram_mem6_RAMD_D1_O has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_completion_info_selectram/Mram_mem5_RAMD_D1_O has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_completion_info_selectram/Mram_mem2_RAMD_D1_O has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_completion_info_selectram/Mram_mem1_RAMD_D1_O has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal i_system/nifsap6/INSTANTIATE_PRODUCERS[0].producer_handler/target_fifo/Mram_fifo_buffer3_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal i_system/nifsap6/INSTANTIATE_PRODUCERS[0].producer_handler/target_fifo/Mram_fifo_buffer2_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal i_system/nifsap6/INSTANTIATE_PRODUCERS[1].producer_handler/target_fifo/Mram_fifo_buffer2_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal i_system/nifsap6/INSTANTIATE_PRODUCERS[1].producer_handler/target_fifo/Mram_fifo_buffer3_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_trn_td_fifo_async_sel/i_fifo_selram/Mram_mem8_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_trn_td_fifo_async_sel/i_fifo_selram/Mram_mem1_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_trn_td_fifo_async_sel/i_fifo_selram/Mram_mem10_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_trn_td_fifo_async_sel/i_fifo_selram/Mram_mem11_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_trn_td_fifo_async_sel/i_fifo_selram/Mram_mem3_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_trn_td_fifo_async_sel/i_fifo_selram/Mram_mem7_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_trn_td_fifo_async_sel/i_fifo_selram/Mram_mem9_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_trn_td_fifo_async_sel/i_fifo_selram/Mram_mem2_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_trn_td_fifo_async_sel/i_fifo_selram/Mram_mem4_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_trn_td_fifo_async_sel/i_fifo_selram/Mram_mem5_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_host_interface/dini_pcie/i_pcie_full_design/i_to_host_tlp_handler/i_trn_td_fifo_async_sel/i_fifo_selram/Mram_mem6_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal i_system/nifsap0/INSTANTIATE_PRODUCERS[0].producer_handler/target_fifo/Mram_fifo_buffer3_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal i_system/nifsap0/INSTANTIATE_PRODUCERS[0].producer_handler/target_fifo/Mram_fifo_buffer2_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal i_system/nifsap0/INSTANTIATE_PRODUCERS[0].producer_handler/target_fifo/Mram_fifo_buffer1_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[17] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[16] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[15] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[14] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[13] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[12] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[11] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[10] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[9] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[8] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[7] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[6] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[5] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[4] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[3] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[2] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[1] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[0] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[17] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[16] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[15] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[14] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[13] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[12] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[11] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[10] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[9] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[8] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[7] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[6] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[5] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[4] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[3] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[2] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[1] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[0] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal i_system/i_pf_skintone_nifsop_1/nif_input_width_select_PROXY has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal i_system/i_pf_skintone_nifsop_1/nif_output_width_select_PROXY has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_input_port/i_output_synchronizer/LBL_TARGET_SRC_FIFO_NON_SEGMENT[0].target_fifo/Mra
   m_fifo_buffer3_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_input_port/i_output_synchronizer/LBL_TARGET_SRC_FIFO_NON_SEGMENT[0].target_fifo/Mra
   m_fifo_buffer1_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_input_port/i_output_synchronizer/LBL_TARGET_SRC_FIFO_NON_SEGMENT[0].target_fifo/Mra
   m_fifo_buffer2_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_1/i_skintone_detector/i_input_port/i_output_synchronizer/LBL_TARGET_SRC_FIFO_NON_SEGMENT[0].target_fifo/Mra
   m_fifo_buffer4_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[17] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[16] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[15] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[14] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[13] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[12] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[11] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[10] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[9] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[8] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[7] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[6] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[5] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[4] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[3] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[2] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[1] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_RY/use_fabric.adder/out_s[0] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[17] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[16] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[15] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[14] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[13] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[12] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[11] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[10] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[9] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[8] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[7] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[6] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[5] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[4] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[3] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[2] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[1] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_rgb2ycrcb/i_rgb2ycrcb_converter/BU2/U0/sub_BY/use_fabric.adder/out_s[0] has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal i_system/i_pf_skintone_nifsop_2/nif_input_width_select_PROXY has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal i_system/i_pf_skintone_nifsop_2/nif_output_width_select_PROXY has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_input_port/i_output_synchronizer/LBL_TARGET_SRC_FIFO_NON_SEGMENT[0].target_fifo/Mra
   m_fifo_buffer1_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_input_port/i_output_synchronizer/LBL_TARGET_SRC_FIFO_NON_SEGMENT[0].target_fifo/Mra
   m_fifo_buffer3_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_input_port/i_output_synchronizer/LBL_TARGET_SRC_FIFO_NON_SEGMENT[0].target_fifo/Mra
   m_fifo_buffer2_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   i_system/i_pf_skintone_nifsop_2/i_skintone_detector/i_input_port/i_output_synchronizer/LBL_TARGET_SRC_FIFO_NON_SEGMENT[0].target_fifo/Mra
   m_fifo_buffer4_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
Starting Router


Phase  1  : 219954 unrouted;      REAL time: 49 mins 37 secs

Phase  2  : 183297 unrouted;      REAL time: 51 mins 2 secs
WARNING:Route:560 - The router has detected an unroutable situation for one or more connections. The cause of this behavior is likely an
   issue with the placement, unroutable placement constraints, or Area Group constraints. To allow you to use FPGA editor to isolate the
   problems, the following is a list of (up to 10) such unroutable connections:
WARNING:Route:561 - The router will finish the rest of the design and leave these unrouted.
     Unroutable      signal: i_host_interface/dini_pcie/ep/pcie_clocking_i/clk_250      pin:
i_host_interface/dini_pcie/ep/pcie_clocking_i/sel_lnk_rate_d/CLK


Phase  3  : 72245 unrouted;      REAL time: 1 hrs 16 mins 28 secs

Phase  4  : 72235 unrouted; (Setup:0, Hold:7861, Component Switching Limit:0)     REAL time: 1 hrs 17 mins 31 secs

Updating file: config_2_routed.ncd with current fully routed design.

Phase  5  : 1 unrouted; (Setup:0, Hold:6229, Component Switching Limit:0)     REAL time: 1 hrs 40 mins 6 secs

Phase  6  : 1 unrouted; (Setup:0, Hold:6229, Component Switching Limit:0)     REAL time: 1 hrs 40 mins 6 secs

Phase  7  : 1 unrouted; (Setup:0, Hold:6229, Component Switching Limit:0)     REAL time: 1 hrs 40 mins 6 secs

Phase  8  : 1 unrouted; (Setup:0, Hold:6229, Component Switching Limit:0)     REAL time: 1 hrs 40 mins 6 secs

Phase  9  : 1 unrouted; (Setup:0, Hold:6229, Component Switching Limit:0)     REAL time: 1 hrs 40 mins 7 secs

Phase 10  : 1 unrouted; (Setup:0, Hold:3753, Component Switching Limit:0)     REAL time: 1 hrs 40 mins 32 secs
WARNING:Route:452 -
    Not all timing constraints have been achieved.  Please consult the `Post-Place & Route Static Timing Report' to determine the actual
   timing results.  For suggestions on how to work around this problem go to http://support.xilinx.com and `Search Answers Database' using
   the text of this message.

Total REAL time to Router completion: 1 hrs 40 mins 46 secs
Total CPU time to Router completion: 18 mins 18 secs

Partition Implementation Status
-------------------------------

  Preserved Partitions:


  Implemented Partitions:

    Partition "/ml605":
Attribute STATE set to IMPLEMENT.

    Partition "/ml605/i_system/i_pf_skintone_nifsop_1" (Reconfigurable Module "pf_skintone_nifsop_1"):
Attribute STATE set to IMPLEMENT.

    Partition "/ml605/i_system/i_pf_skintone_nifsop_2" (Reconfigurable Module "pf_skintone_nifsop_2"):
Attribute STATE set to IMPLEMENT.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       client0_clock | BUFGCTRL_X0Y8| No   | 4944 |  0.461     |  2.048      |
+---------------------+--------------+------+------+------------+-------------+
|          host_clock |BUFGCTRL_X0Y30| No   | 4323 |  0.440     |  2.020      |
+---------------------+--------------+------+------+------------+-------------+
|i_host_interface/din |              |      |      |            |             |
|  i_pcie/ep/pipe_clk | BUFGCTRL_X0Y2| No   |  205 |  0.392     |  2.046      |
+---------------------+--------------+------+------+------------+-------------+
|i_host_interface/din |              |      |      |            |             |
|  i_pcie/ep/user_clk | BUFGCTRL_X0Y1| No   |  269 |  0.290     |  1.934      |
+---------------------+--------------+------+------+------------+-------------+
|i_host_interface/din |              |      |      |            |             |
|i_pcie/ep/TxOutClk_b |              |      |      |            |             |
|                 ufg | BUFGCTRL_X0Y0| No   |    6 |  0.012     |  1.617      |
+---------------------+--------------+------+------+------------+-------------+
|i_host_interface/din |              |      |      |            |             |
|   i_pcie/ep/drp_clk | BUFGCTRL_X0Y4| No   |   17 |  0.394     |  2.046      |
+---------------------+--------------+------+------+------------+-------------+
|MMCM_PHASE_CALIBRATI |              |      |      |            |             |
|ON_ML_LUT2_12_ML_NEW |              |      |      |            |             |
|                _CLK |         Local|      |    3 |  0.124     |  0.361      |
+---------------------+--------------+------+------+------------+-------------+
|i_mmcm_fpga_top/mmcm |              |      |      |            |             |
| _adv_inst_ML_NEW_I1 |         Local|      |    3 |  0.000     |  1.551      |
+---------------------+--------------+------+------+------------+-------------+
|MMCM_PHASE_CALIBRATI |              |      |      |            |             |
|ON_ML_LUT2_20_ML_NEW |              |      |      |            |             |
|                _CLK |         Local|      |    3 |  0.000     |  0.364      |
+---------------------+--------------+------+------+------------+-------------+
|i_host_interface/din |              |      |      |            |             |
|i_pcie/ep/pcie_clock |              |      |      |            |             |
|ing_i/mmcm_adv_i_ML_ |              |      |      |            |             |
|              NEW_I1 |         Local|      |    3 |  0.000     |  1.743      |
+---------------------+--------------+------+------+------------+-------------+
|MMCM_PHASE_CALIBRATI |              |      |      |            |             |
|ON_ML_LUT2_28_ML_NEW |              |      |      |            |             |
|                _CLK |         Local|      |    2 |  0.000     |  0.475      |
+---------------------+--------------+------+------+------------+-------------+
|i_host_interface/din |              |      |      |            |             |
|i_pcie/i_clocks_rese |              |      |      |            |             |
|ts/i_pll_user_clk_ML |              |      |      |            |             |
|             _NEW_I1 |         Local|      |    3 |  0.000     |  1.702      |
+---------------------+--------------+------+------+------------+-------------+
|i_host_interface/din |              |      |      |            |             |
|i_pcie/i_clocks_rese |              |      |      |            |             |
|ts/i_pll_user_clk_ML |              |      |      |            |             |
|            _NEW_OUT |         Local|      |    2 |  0.000     |  0.365      |
+---------------------+--------------+------+------+------------+-------------+
|i_host_interface/din |              |      |      |            |             |
|i_pcie/ep/pcie_clock |              |      |      |            |             |
|ing_i/mmcm_adv_i_ML_ |              |      |      |            |             |
|             NEW_OUT |         Local|      |    2 |  0.000     |  0.540      |
+---------------------+--------------+------+------+------------+-------------+
|i_mmcm_fpga_top/mmcm |              |      |      |            |             |
|_adv_inst_ML_NEW_OUT |              |      |      |            |             |
|                     |         Local|      |    2 |  0.000     |  0.497      |
+---------------------+--------------+------+------+------------+-------------+
|i_host_interface/din |              |      |      |            |             |
|i_pcie/ep/pcie_clock |              |      |      |            |             |
|      ing_i/clk_250* |         Local|      |    3 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|i_host_interface/din |              |      |      |            |             |
|i_pcie/pcie_finger_r |              |      |      |            |             |
|              ef_clk |         Local|      |    8 |  0.000     |  1.600      |
+---------------------+--------------+------+------+------------+-------------+
* Some of the Clock networks are NOT completely routed

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 3753 (Setup: 0, Hold: 3753, Component Switching Limit: 0)

WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in your design.

   Review the timing report using Timing Analyzer (In ISE select "Post-Place &
   Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.

   Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
   are set in the tools for timing closure.

   Increase the PAR Effort Level setting to "high"

   Reference the design closure chapter in ISE Help

   Visit the Xilinx technical support web at http://support.xilinx.com and go to
   either "Troubleshoot->Tech Tips->Timing & Constraints" or "
   TechXclusives->Timing Closure" for tips and suggestions for meeting timing
   in your design.

Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
* TS_i_mmcm_fpga_top_clkout3 = PERIOD TIMEG | SETUP       |     0.188ns|     9.812ns|       0|           0
  RP "i_mmcm_fpga_top_clkout3"         TS_S | HOLD        |    -0.112ns|            |     116|        3753
  YS_CLK / 0.5 HIGH 50%                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_SYS_CLK = PERIOD TIMEGRP "TNM_SYS_CLK" | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0
   5 ns HIGH 50%                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_pcie_fifos_delay_path" TIG       | SETUP       |         N/A|     2.294ns|     N/A|           0
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_SYS_CLK
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SYS_CLK                     |      5.000ns|      2.800ns|      4.906ns|            0|          116|            0|       846278|
| TS_i_mmcm_fpga_top_clkout3    |     10.000ns|      9.812ns|          N/A|          116|            0|       846278|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
   constraint is not analyzed due to the following: No paths covered by this
   constraint; Other constraints intersect with this constraint; or This
   constraint was disabled by a Path Tracing Control. Please run the Timespec
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

1 signals are not completely routed. See the config_2_routed.unroutes file for a list of all unrouted signals.

WARNING:Par:100 - Design is not completely routed. There are 1 signals that are not
   completely routed in this design. See the "config_2_routed.unroutes" file for a list of
   all unrouted signals. Check for other warnings in your PAR report that might
   indicate why these nets are unroutable. These nets can also be evaluated
   in FPGA Editor by selecting "Unrouted Nets" in the List Window.

WARNING:Par:283 - There are 111 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 1 hrs 52 mins 5 secs
Total CPU time to PAR completion: 19 mins 1 secs

Peak Memory Usage:  1091 MB

Placer: Placement generated during map.
Routing: Completed - errors found.
Timing: Completed - 116 errors found.

Number of error messages: 0
Number of warning messages: 119
Number of info messages: 0

Writing design to file config_2_routed.ncd



PAR done!


0 Kudos
woodsd
Xilinx Employee
Xilinx Employee
16,087 Views
Registered: ‎04-16-2008

It looks like the clock that is not routing is on local routing.  If this feeds the RM, this clock is probably getting a PROXY LUT inferred on it.  Try making sure all of the clocks reported by PAR are on BUFGs (no "local").  Also, you can open this design in FPGA Editor and look at the source/destination of this unrouted net.  This will probably become clear why it can't be routed. 

0 Kudos
siddadd
Observer
Observer
16,083 Views
Registered: ‎04-03-2012

In my constraint file, the MMCM placement has been given as follows:

 

Constraint file

# MMCM Placment. This constraint selects the MMCM Placement

INST "*/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7;

 

However, when I opened up the design in FPGA editor, I notice that the clock that is not routing is getting allocated to MMCM_ADV_X0Y4 (Attached screenshot) instead.

 

I am not sure why this is happening. Does it have to do with where I am placing my pblocks for the RMs? I did notice that the number of timing errors is a function of where I place my RM pblocks.

0 Kudos
woodsd
Xilinx Employee
Xilinx Employee
16,078 Views
Registered: ‎04-16-2008

If you are using planAhead, make sure PlanAhead isn't dropping your MMCM LOC constraint.  You can view the Tcl Console for messages.  Also, make sure the "config_1.ucf" in the "./runs/config_1" directory still has this constraint.  You may want to try using PlanAhead to LOC these to make sure the syntax is correct, and that the full hierarchical name is specified (no wildcards).  

 

However, the issue I was hinting at is not the location of the MMCM, but a missing BUFG.  If the MMCM output does not drive a BUFG, then the clock will be local.  If the clock is locally routed it will get a PROXY LUT inferred, and the MMCM output probably has no routing access to a LUT input.  Hence why the clock is unrouted.

 

 

siddadd
Observer
Observer
16,068 Views
Registered: ‎04-03-2012

You were right. The MMCM LOC constraint is not there in Plan Ahead's version of the file (config_1.ucf)

 

Basically, we are using a dini_pcie module that is an encrypted black box and the MMCM LOC constraint is for this module. We believe Plan Ahead is unable to see the encryption ahead of time and maybe that is why it is wiping out the constraint. Is there any way to work around this?

 

The problem with the unrouted clk is still not found. We checked the MAP report and it doesnt mention any discrepancy.

 

######################################################################################
# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:
#
# Number of Global Clock Regions : 12
# Number of Global Clock Networks: 11
#
# Clock Region Assignment: SUCCESSFUL

# Location of Clock Components
INST "i_mmcm_fpga_top/clkf_buf" LOC = "BUFGCTRL_X0Y5" ;
INST "i_host_interface/dini_pcie/internal_reset_BUFG" LOC = "BUFGCTRL_X0Y29" ;
INST "i_host_interface/dini_pcie/ep/pcie_clocking_i/clkfbin_bufg_i" LOC = "BUFGCTRL_X0Y3" ;
INST "i_host_interface/dini_pcie/ep/pcie_clocking_i/x4_GEN2_250_00.user_clk_bufg" LOC = "BUFGCTRL_X0Y1" ;
INST "i_host_interface/dini_pcie/i_clocks_resets/i_bufg_internal_clk" LOC = "BUFGCTRL_X0Y30" ;
INST "i_host_interface/dini_pcie/ep/pcie_clocking_i/sys_clk_bufg_i" LOC = "BUFGCTRL_X0Y0" ;
INST "i_mmcm_fpga_top/clkout1_buf" LOC = "BUFGCTRL_X0Y6" ;
INST "i_mmcm_fpga_top/clkout3_buf" LOC = "BUFGCTRL_X0Y7" ;
INST "i_mmcm_fpga_top/clkout4_buf" LOC = "BUFGCTRL_X0Y8" ;
INST "i_mmcm_fpga_top/clkout5_buf" LOC = "BUFGCTRL_X0Y9" ;
INST "i_host_interface/dini_pcie/ep/pcie_clocking_i/GEN2_LINK.pipe_clk_bufgmux" LOC = "BUFGCTRL_X0Y2" ;
INST "i_host_interface/dini_pcie/i_clocks_resets/i_bufg_user_clk_fb" LOC = "BUFGCTRL_X0Y31" ;
INST "i_host_interface/dini_pcie/ep/pcie_clocking_i/drp_clk_bufg_i" LOC = "BUFGCTRL_X0Y4" ;
INST "sys_clk_p" LOC = "J9" ;
INST "i_host_interface/dini_pcie/i_clocks_resets/i_ibufds_clk_gtp" LOC = "IBUFDS_GTXE1_X0Y4" ;
INST "i_host_interface/dini_pcie/ep/pcie_clocking_i/mmcm_adv_i" LOC = "MMCM_ADV_X0Y4" ;
INST "i_host_interface/dini_pcie/i_clocks_resets/i_pll_user_clk" LOC = "MMCM_ADV_X0Y11" ;
INST "i_mmcm_fpga_top/mmcm_adv_inst" LOC = "MMCM_ADV_X0Y0" ;
INST "i_host_interface/dini_pcie/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC = "GTXE1_X0Y10" ;
INST "i_host_interface/dini_pcie/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX" LOC = "GTXE1_X0Y9" ;
INST "i_host_interface/dini_pcie/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX" LOC = "GTXE1_X0Y11" ;
INST "i_host_interface/dini_pcie/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX" LOC = "GTXE1_X0Y8" ;

# i_mmcm_fpga_top/clkfbout_buf driven by BUFGCTRL_X0Y5
NET "i_mmcm_fpga_top/clkfbout_buf" TNM_NET = "TN_i_mmcm_fpga_top/clkfbout_buf" ;
TIMEGRP "TN_i_mmcm_fpga_top/clkfbout_buf" AREA_GROUP = "CLKAG_i_mmcm_fpga_top/clkfbout_buf" ;
AREA_GROUP "CLKAG_i_mmcm_fpga_top/clkfbout_buf" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;

# i_host_interface/dini_pcie/internal_reset_BUFG driven by BUFGCTRL_X0Y29
NET "i_host_interface/dini_pcie/internal_reset_BUFG" TNM_NET = "TN_i_host_interface/dini_pcie/internal_reset_BUFG" ;
TIMEGRP "TN_i_host_interface/dini_pcie/internal_reset_BUFG" AREA_GROUP = "CLKAG_i_host_interface/dini_pcie/internal_reset_BUFG" ;
AREA_GROUP "CLKAG_i_host_interface/dini_pcie/internal_reset_BUFG" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;

# i_host_interface/dini_pcie/ep/pcie_clocking_i/mmcm_clkfbin driven by BUFGCTRL_X0Y3
NET "i_host_interface/dini_pcie/ep/pcie_clocking_i/mmcm_clkfbin" TNM_NET = "TN_i_host_interface/dini_pcie/ep/pcie_clocking_i/mmcm_clkfbin" ;
TIMEGRP "TN_i_host_interface/dini_pcie/ep/pcie_clocking_i/mmcm_clkfbin" AREA_GROUP = "CLKAG_i_host_interface/dini_pcie/ep/pcie_clocking_i/mmcm_clkfbin" ;
AREA_GROUP "CLKAG_i_host_interface/dini_pcie/ep/pcie_clocking_i/mmcm_clkfbin" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;

# i_host_interface/dini_pcie/ep/user_clk driven by BUFGCTRL_X0Y1
NET "i_host_interface/dini_pcie/ep/user_clk" TNM_NET = "TN_i_host_interface/dini_pcie/ep/user_clk" ;
TIMEGRP "TN_i_host_interface/dini_pcie/ep/user_clk" AREA_GROUP = "CLKAG_i_host_interface/dini_pcie/ep/user_clk" ;
AREA_GROUP "CLKAG_i_host_interface/dini_pcie/ep/user_clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;

# host_clock driven by BUFGCTRL_X0Y30
NET "host_clock" TNM_NET = "TN_host_clock" ;
TIMEGRP "TN_host_clock" AREA_GROUP = "CLKAG_host_clock" ;
AREA_GROUP "CLKAG_host_clock" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;

# i_host_interface/dini_pcie/ep/TxOutClk_bufg driven by BUFGCTRL_X0Y0
NET "i_host_interface/dini_pcie/ep/TxOutClk_bufg" TNM_NET = "TN_i_host_interface/dini_pcie/ep/TxOutClk_bufg" ;
TIMEGRP "TN_i_host_interface/dini_pcie/ep/TxOutClk_bufg" AREA_GROUP = "CLKAG_i_host_interface/dini_pcie/ep/TxOutClk_bufg" ;
AREA_GROUP "CLKAG_i_host_interface/dini_pcie/ep/TxOutClk_bufg" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;

# client0_clock driven by BUFGCTRL_X0Y8
NET "client0_clock" TNM_NET = "TN_client0_clock" ;
TIMEGRP "TN_client0_clock" AREA_GROUP = "CLKAG_client0_clock" ;
AREA_GROUP "CLKAG_client0_clock" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;

# i_host_interface/dini_pcie/ep/pipe_clk driven by BUFGCTRL_X0Y2
NET "i_host_interface/dini_pcie/ep/pipe_clk" TNM_NET = "TN_i_host_interface/dini_pcie/ep/pipe_clk" ;
TIMEGRP "TN_i_host_interface/dini_pcie/ep/pipe_clk" AREA_GROUP = "CLKAG_i_host_interface/dini_pcie/ep/pipe_clk" ;
AREA_GROUP "CLKAG_i_host_interface/dini_pcie/ep/pipe_clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;

# i_host_interface/dini_pcie/i_clocks_resets/user_clk_fb_in driven by BUFGCTRL_X0Y31
NET "i_host_interface/dini_pcie/i_clocks_resets/user_clk_fb_in" TNM_NET = "TN_i_host_interface/dini_pcie/i_clocks_resets/user_clk_fb_in" ;
TIMEGRP "TN_i_host_interface/dini_pcie/i_clocks_resets/user_clk_fb_in" AREA_GROUP = "CLKAG_i_host_interface/dini_pcie/i_clocks_resets/user_clk_fb_in" ;
AREA_GROUP "CLKAG_i_host_interface/dini_pcie/i_clocks_resets/user_clk_fb_in" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;

# i_host_interface/dini_pcie/ep/drp_clk driven by BUFGCTRL_X0Y4
NET "i_host_interface/dini_pcie/ep/drp_clk" TNM_NET = "TN_i_host_interface/dini_pcie/ep/drp_clk" ;
TIMEGRP "TN_i_host_interface/dini_pcie/ep/drp_clk" AREA_GROUP = "CLKAG_i_host_interface/dini_pcie/ep/drp_clk" ;
AREA_GROUP "CLKAG_i_host_interface/dini_pcie/ep/drp_clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;

# i_host_interface/dini_pcie/ep/pcie_clocking_i/clk_250 driven by MMCM_ADV_X0Y4
NET "i_host_interface/dini_pcie/ep/pcie_clocking_i/clk_250" TNM_NET = "TN_i_host_interface/dini_pcie/ep/pcie_clocking_i/clk_250" ;
TIMEGRP "TN_i_host_interface/dini_pcie/ep/pcie_clocking_i/clk_250" AREA_GROUP = "CLKAG_i_host_interface/dini_pcie/ep/pcie_clocking_i/clk_250" ;
AREA_GROUP "CLKAG_i_host_interface/dini_pcie/ep/pcie_clocking_i/clk_250" RANGE =   CLOCKREGION_X1Y2 ;

# NOTE:
# This report is provided to help reproduce successful clock-region
# assignments. The report provides range constraints for all global
# clock networks, in a format that is directly usable in ucf files.
#
#END of Global Clock Net Distribution UCF Constraints
######################################################################################

 

I opened up FPGA editor and zoomed in on the unrouted clk signal mentioned in the PAR report. Seems to be a BUFG inferred for it. (screenshot attached)

 

1 signals are not completely routed.

WARNING:ParHelpers:360 - Design is not completely routed.

   i_host_interface/dini_pcie/ep/pcie_clocking_i/clk_250
WARNING:ParHelpers:361 - There are 111 loadless signals in this design. This design will cause Bitgen to issue DRC
   warnings.

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siddadd
Observer
Observer
16,060 Views
Registered: ‎04-03-2012

I removed the dini_pcie module and ran Plan Ahead successively without any PAR failures.

 

So it seems that Plan Ahead does not like the fact that the dini_pcie module is an encrypted black box.

 

Is there any work around that will allow dini_pcie and Plan Ahead to be compatable?

 

 

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woodsd
Xilinx Employee
Xilinx Employee
16,058 Views
Registered: ‎04-16-2008

I don't understand the failure, so I can't say for sure.  If the issue is simply constraitns being dropped, then the solution is to put these constraitns in a separate UCF file and do NOT add them to the PlanAhead Project.  Instead modify your implementation strategy and under the "other options" field for NGDBuild add a "-uc" switch that points to your other UCF:

 

-uc ../../dini_pcie.ucf

 

This will prevent planAhead from processing and dropping constraints related to this module, but will pass this on to NGDBuild.

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