cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
abanaiyan
Visitor
Visitor
13,560 Views
Registered: ‎07-11-2013

Partial Reconfiguration: PlanAhead exception error

Jump to solution

Hi,

 

I am using PlamAhead 14.4 for PR.

I successfully implemented and tested Xilinx XAPP883 reference design.

Now, I am trying to implement my own design in the same environemnt. I successfully can run config1 to completion of PAR. Then, when I try to run config2, an exception is occured and PalanAhead is terminated. 

 

Here is the last sentences in planahead.log: 

 

Loading device configuration modes from /opt/Xilinx/14.4/ISE_DS/PlanAhead/data/parts/xilinx/virtex6/ConfigModes.xml
Loading list of drcs for the architecture : /opt/Xilinx/14.4/ISE_DS/PlanAhead/data/./parts/xilinx/virtex6/drc.xml
Parsing UCF File [/home/abbas/speedy-partition/hw/planahead/project_1/project_1.srcs/constrs_1/imports/UCF/XAPP883_bee4_lx240t_gen2x8.ucf]
Finished Parsing UCF File [/home/abbas/speedy-partition/hw/planahead/project_1/project_1.srcs/constrs_1/imports/UCF/XAPP883_bee4_lx240t_gen2x8.ucf]

 

CRITICAL WARNING: [Netlist 29-33] While transforming instance 'PCM_CK0' of type 'OBUFDS_DUAL_BUF', an exception was caught: 'ERROR: [Common 17-70] Application Exception: Netlist Transformation: new instance for SINGLE_BUF is NULL'
This instance will be converted to a black box element.

 


Note that I am using different buffers in my top module such as IBUF, IOBUF, OBUF, and IBUFDS_GTXE1and none of them cause an exception. The OBUFDS is only the one causes exception error! If I comment out this buffer instansiation in my top module, it will be run without exception!!

 

OBUFDS PCM_CK0 (
.I(pcm_clock),
.O(CLK_PCM_P),
.OB(CLK_PCM_N) );

 

 

Any help would be appreciated.

Thanks,

Abbas

0 Kudos
1 Solution

Accepted Solutions
vemulad
Xilinx Employee
Xilinx Employee
20,729 Views
Registered: ‎09-20-2012

Hello Abbas,

 

A warm welcome to Xilinx Forums.

 

What is the IO standard specified for output ports of OBUFDS primitive?

 

Try disabling the parameter  as shown below and then run the Implementation. Type the below command in to Planahead TCL console.

 

set_param funnel.forceHierarchy FALSE

 

We have seen few issues before where the tool was giving the same warning message. The above parameter helped to overcome the issue in those cases. Let us know if this helps.

 

Regards,

Deepika.

 

 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

4 Replies
vemulad
Xilinx Employee
Xilinx Employee
20,730 Views
Registered: ‎09-20-2012

Hello Abbas,

 

A warm welcome to Xilinx Forums.

 

What is the IO standard specified for output ports of OBUFDS primitive?

 

Try disabling the parameter  as shown below and then run the Implementation. Type the below command in to Planahead TCL console.

 

set_param funnel.forceHierarchy FALSE

 

We have seen few issues before where the tool was giving the same warning message. The above parameter helped to overcome the issue in those cases. Let us know if this helps.

 

Regards,

Deepika.

 

 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

abanaiyan
Visitor
Visitor
13,541 Views
Registered: ‎07-11-2013

Deepika,

 

It resolved the problem.

 

Thanks for your help.

 

Best,

Abbas

0 Kudos
vemulad
Xilinx Employee
Xilinx Employee
13,534 Views
Registered: ‎09-20-2012
Hi,

Thats great. I am marking this thread as solved.

Cheers,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
tuan_nus
Visitor
Visitor
12,131 Views
Registered: ‎06-30-2014

Hi vemulad, 

 

I'm using 14.7 and ML605 board, I followed your instruction to set the parameter in planAhead:

 

set_param funnel.forceHierarchy FALSE
 

Unfortunately, the problem persists but in a weird way. For every blackbox module, the first time I set it as PR module and assign the first variant, i.e netlist, the planAhead crashes with the same error:
 
CRITICAL WARNING: [Netlist 29-33] While transforming instance 'DDR3_SDRAM/mpmc_core_0/gen_v6_ddr3_phy.mpmc_phy_if_0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob/u_obuf_ck' of type 'OBUFDS_DUAL_BUF', an exception was caught: 'ERROR: [Common 17-70] Application Exception: Netlist Transformation: new instance for SINGLE_BUF is NULL

 

Then I have to open planAhead again and add remaining variants for that PR module, this time, planAhead does not crash. After that, I move on to the next blackbox, assign the first varient, it stops the same way. If I have n blackboxes in the system, planAhead will crash times since I have to configure blackboxes as PR modules.

 

Fortunately, the final bit files generated by planAhead work without problem. 

 

It's irritating, can you help me to identify the problem? I use the same constraints for DDR3 as generated by XPS BSB. 

 

Thank you very much!

 

Tuan Nguyen

 


0 Kudos