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Participant ccdoss
Participant
1,452 Views
Registered: ‎10-24-2008

Partial Reconfiguration from Block Diagram IP

I've created a simple block diagram of my application, which includes my custom IP. I'd like for my custom IP to be reconfigurable, while the remaining elements in the design remain static. However, it appears we can't do this using block diagram sources. When I try to put my IP into a RM, Vivado says I need to create an RTL wrapper for the module. However, this isn't available.

 

Is it possible to do partial reconfiguration from a design created through the block diagram? Or must I abandon all of the benefits of creating something within the block diagram flow in order to do partial reconfiguration?

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5 Replies
Moderator
Moderator
1,358 Views
Registered: ‎11-04-2010

Re: Partial Reconfiguration from Block Diagram IP

Hi, @ccdoss ,
What's the mode do you use for the PR flow? Project mode or non-project mode?
If you are using project mode:
Block Diagrams cannot be included as RMs or within RMs.
Modules within Block Diagrams cannot be set as RMs.
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Participant ccdoss
Participant
1,334 Views
Registered: ‎10-24-2008

Re: Partial Reconfiguration from Block Diagram IP

I guess I'm in project mode. 

 

I realize that I can't use BD's for partial reconfiguration. However, given the ease at which I can instantiate PCIe and AXI peripherals with BD, especially some of the behind-the-scenes stuff it does, I was hoping I wouldn't have to redo the design from scratch in VHDL.

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Moderator
Moderator
1,326 Views
Registered: ‎11-04-2010

Re: Partial Reconfiguration from Block Diagram IP

Hi, @ccdoss ,

IP Integrator support is not in place in the project-mode. Block Diagrams cannot be included as RMs or within RMs. Modules within Block Diagrams cannot be set as RMs.

If you intend to apply block-design in PR flow, you have to turn to non-project mode. You can begin with Lab2 in UG947.

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Participant ccdoss
Participant
1,317 Views
Registered: ‎10-24-2008

Re: Partial Reconfiguration from Block Diagram IP

I have taken a look at it, and have a couple of follow-up questions:

1. Are you saying I can start off with a BD, and then follow the tutorial? I'm a little confused on the entry point.

2. I'm not using one of the boards mentioned in the tutorial, and not one sold by Xilinx. Will this cause any problems?

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Moderator
Moderator
1,312 Views
Registered: ‎11-04-2010

Re: Partial Reconfiguration from Block Diagram IP

1. What I mean is that you can use BD to generate the netlist(DCP) of Static logic or RM. Then you can refer to the steps in the lab to combine these DCP files in the non-project mode.
2. Using which board in tutorial is not important. The main purpose is to show you the example command in PR design.
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