07-16-2018 02:31 PM
I've created a simple block diagram of my application, which includes my custom IP. I'd like for my custom IP to be reconfigurable, while the remaining elements in the design remain static. However, it appears we can't do this using block diagram sources. When I try to put my IP into a RM, Vivado says I need to create an RTL wrapper for the module. However, this isn't available.
Is it possible to do partial reconfiguration from a design created through the block diagram? Or must I abandon all of the benefits of creating something within the block diagram flow in order to do partial reconfiguration?
07-21-2018 10:21 AM
07-23-2018 10:49 AM
I guess I'm in project mode.
I realize that I can't use BD's for partial reconfiguration. However, given the ease at which I can instantiate PCIe and AXI peripherals with BD, especially some of the behind-the-scenes stuff it does, I was hoping I wouldn't have to redo the design from scratch in VHDL.
07-23-2018 07:06 PM
Hi, @ccdoss ,
IP Integrator support is not in place in the project-mode. Block Diagrams cannot be included as RMs or within RMs. Modules within Block Diagrams cannot be set as RMs.
If you intend to apply block-design in PR flow, you have to turn to non-project mode. You can begin with Lab2 in UG947.
07-24-2018 06:53 AM
I have taken a look at it, and have a couple of follow-up questions:
1. Are you saying I can start off with a BD, and then follow the tutorial? I'm a little confused on the entry point.
2. I'm not using one of the boards mentioned in the tutorial, and not one sold by Xilinx. Will this cause any problems?
07-24-2018 07:58 AM