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Observer johnli
Observer
290 Views
Registered: ‎08-10-2011

Partial Reconfiguration: need select IOB insertion to avoid [DRC HDPR-6]

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Hi, I need some help on partition I/Os for PR :

I follow page 44 - 45 of the PR guide(UG909, 2018.3) for my Ultrascale+/ICAP project. At some stage I encountered these errors after I added I/O, GTH in my reconfigurable module. Here is what I get:

ERROR: [DRC HDPR-6] Logic illegally placed: Cell 'scl_OBUF_inst' is placed at site 'IOB_X0Y47' which belongs to reconfigurable Pblock 'pb_app'. This cell is not part of the reconfigurable logic assigned to this Pblock, and should not be placed at this site.
ERROR: [DRC REQP-1927] IBUFDS_GTE4_connects_I_active: IBUFDS_GTE4 app/gtclk_ibuf pin I has an invalid driver gtclk_p_IBUF_inst/IBUFCTRL_INST. Only a direct connection to a Port may drive the IBUFDS_GTE4 pin.

My design has these files:

top_synth.dcp : top level with blackbox for app module. Not OOC, so all IOBs are inserted.

app_ooc.dcp: RM module for cell "app", OOC, with 95% ports to top and 5% to chip I/O pins.

top_impl.xdc: contain pb_app for app and all package pins. I checked only IO pins for app are in pb_app, others are in top.

I understand the above errors, but would like to know how do I insert selected IOBs to my app_ooc.dcp, and the rest in top during synthesis/implementation. What I can think of is set IO_BUFFER_TYPE = "none" in their HDL files, and don't use OOC. Are there other better ways? How about the IOB_CTRL premitives that usually get generated? like GTH clocks (inside PR module).

Please Help.

John

 

 

 

 

 

 

 

 

 

ASIC & FPGA/SoC designer
NYC HPC
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1 Solution

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Xilinx Employee
Xilinx Employee
263 Views
Registered: ‎01-30-2019

Re: Partial Reconfiguration: need select IOB insertion to avoid [DRC HDPR-6]

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@johnli 

Following are my suggestions,

as per UG901, page 37 important note

Capture.JPG

 

while using out-of-context mode for a submodule in the hierarchy, if you instantiate the buffers for the ports of your choice in the RTL of the submodule,

the tool will insert IO buffer on the ports on which you have instantiated buffer and disable insertion of IO ports on the remaining ports.

With this approach, you can control IO Buffers on the submodule ports while using OOC.

--Suraj

3 Replies
Xilinx Employee
Xilinx Employee
264 Views
Registered: ‎01-30-2019

Re: Partial Reconfiguration: need select IOB insertion to avoid [DRC HDPR-6]

Jump to solution

@johnli 

Following are my suggestions,

as per UG901, page 37 important note

Capture.JPG

 

while using out-of-context mode for a submodule in the hierarchy, if you instantiate the buffers for the ports of your choice in the RTL of the submodule,

the tool will insert IO buffer on the ports on which you have instantiated buffer and disable insertion of IO ports on the remaining ports.

With this approach, you can control IO Buffers on the submodule ports while using OOC.

--Suraj

Observer johnli
Observer
255 Views
Registered: ‎08-10-2011

Re: Partial Reconfiguration: need select IOB insertion to avoid [DRC HDPR-6]

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Thank you, I've tried:

1. Insert all IOB in RM inside RTL, run ooc.

2. Mark IO_BUFFER_TYPE="none" in top level.

Looks like full place and route finished (For 1 RM and top).

There are some xdc warning and timing issues when I load locked static implement a different RM.

I will read a bit more and use another question to ask, you can close this.

 

 

ASIC & FPGA/SoC designer
NYC HPC
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Xilinx Employee
Xilinx Employee
223 Views
Registered: ‎01-30-2019

Re: Partial Reconfiguration: need select IOB insertion to avoid [DRC HDPR-6]

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@johnli 

you need to close this thread by accepting the post as solution'

--Suraj

 

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