06-16-2021 05:33 AM
I have a need for a small static design which will maintain an output signal when the FPGA is reloaded and want to use the rest for the FPGA for the rest of the project. There will be no connections between this static logic and the rest of the FPGA other than a shared clock. Is this possible to do using a partial reconfig ?
06-16-2021 06:06 AM
It looks ok to use DFX(PR) flow for the application, and you can have more information from UG909.
06-16-2021 07:51 AM
In addition to UG909 suggested above, other recourses that might be helpful can be found here:
06-16-2021 12:39 PM
In UG909 pg 52 Defining Reconfigurable Partitions, it says suitable instances within the design hierarchy are that Do NOT contain block diagram (.bd) sources. So if the design contains a .bd file this won't work ?
06-16-2021 01:26 PM
For now it wont work, however with the 2021.1 release there will be a feature call Block Design Containers for DFX so stay tuned for that as the release is due this month.
06-16-2021 07:09 PM
Hi, @bfrantz ,
If you are using non-project mode, you just need to create dcp netlist for the Reconfigurable Module(RM), which can also be designed with BD.
BD limitation is just in Project-mode.
06-18-2021 07:37 AM - edited 06-18-2021 10:20 AM
I can certainly use non-project mode. Is there a simple example I could obtain because this is a daunting task since I have never done this before. Additionally, my requirements are sort of the opposite of a typical partial re-config because my static design will be very small like a simple counter and the rest of the design will be the re-config. As such I would like to assign the rest of the FPGA for the reconfig if possible. I am not sure how to do that in non-project mode.
06-20-2021 07:17 PM
You can refer to UG947 for the example designs. If you meet the issue, we can continue to help you in the new posts.