I have two RM blocks. First one has BRAM initialization and the second one has few logics but no BRAM. The static part of the design has UART for communication. Individually these RM modules work perfectly. Here is the situation:
1. First, I loaded the RM module that has BRAM
2. Second, I loaded the RM without any BRAM. Since it has only logic it should power down the BRAM that was used by the previous block right?
3. Third, I loaded the RM one but this time it has no initial value (I deleted the initialization block from the bitstream). It should turn on the BRAM again and read uninitialized values from it. But, I see the previous values. That's a little confusing.
In the second stage, the BRAM should be not be ON and so the data should be gone too. Is it possible that the new partial bitstream does not configure the uninstantiated resources, for instance, BRAM? Is it not a security risk then? Because I use one RM to read another RMs values that are stored in the BRAM. I am using Artix-7. When it comes to power gating is there any difference between Zynq 7020 and Artix-7.