07-28-2011 11:12 AM
I'm trying to perform partial reconfiguration using the Multiboot technique. I worked through XAPP1100 (MultiBoot with Virtex-5 FPGAs and platform Flash XL) and I have a good idea how it is working. However, I'm unable to achieve this reconfiguration on my ML507 development board using ICAP. I tried using the platform flash, but it seems I am unable to do this, due to the dip switch setting the reconfiguration from the platform flash. I then tried to add SPI flash in iMPACT to try and reconfigure from there, but still nothing.
The one thing I don't truly understand is the WBSTAR register is used to set the address of the next bitstream to be loaded. How do I set the specific memory space the bitstream is loaded? The development board is equipped with various memory spaces. How does the ICAP determine where the start address is located?
07-28-2011 12:56 PM
ICAP is nothing but an internal means to access the existing configurtion pins.
There is a "set frame address" command that needs to be in any bitstream (partial or not), along with all of the other commands, and of course, the data to be placed in the configuration memory.
Fetching the data to be sent to ICAP, and managing the process requires either a hardware state machine, and all the interface (to where the fetched data comes from), or the use of a processor (like MicroBlaze) and a c program, AND the logic and interface to the source (memory) with the partial bistream to be loaded.
07-29-2011 12:31 AM
depending on what you want, you can choose either microblaze or state machine to controle your partial reconfiguration.
If you want speed (i.e a very little reconfiguration time), do not use a microblaze, you will lost a lot of clock cycles because of bus latency.
If speed is not a problem and you just want the functionnality, use a microblaze, it is easier to implement.
I am currently write a paper to implement this functionnality in hardware.
For your ML507, depending on which memory you want to use, you will be perhaps modify the CPLD functionnality... Before beginning your code, implement the multiboot with the BPI, understand how works the BPI with ICAP check also CCLK during reconfiguration and after. In fact before beginning a 100% hardware PR design you have to understand how works the configuration interfaces.
I can just assure you that the functionnality works fine with XCF32P and BPI memory on ML507, I implemented it.
Today is my last day internship so I will not answer on the forum for a little time :)
07-29-2011 12:48 AM
sorry for double post,
Concerning the Multiboot feature, you have in the state machine an initialization sequence with a sync_word, a start_address and an IPROG command. The sync_word is to "activate" ICAP interface. The start adress is sent to the WBSTAR which retains the adress you put and after sending Iprog command FPGA go in the memory and load the bitstream stored at the address WBSTAR. In XAPP it tells you can put 4 configuration because of the 2 pins RS. In fact you can put up to 8 V5FX70T bitstream in the BPI memory.
07-29-2011 03:01 AM
Thanks for the reply guys.
I'm using a similar statemachine as given in XAPP1100 reference design to try and reconfigure; thus I'm trying to reconfigure using hardware.
Thanks Austin for explaining the concept of the frame address. However, I think I was a bit unclear asking my question. Let me rephrase. I loaded the bitstream in the XCF32P and BPI, which are different memory spaces. In both cases the initial bitstream is located at 0x00000000 and the second (partial) bitstream at a location after the initial bitstream. For argument's sake, let say I load WBSTAR with the initial address of 0x00000000, which is supposed to be the next bistream loaded. How does WBSTAR determine if this address located in XCF32P or BPI?
@Lammonis, thanks for clarifying the implementation on the ML507 board. The reason why I was unable to reconfigure from XCF32P is because I didn't change the CPLD functionality. I guess it is a lot simpler reconfiguring from the BPI since I don't have to modify the CPLD.
07-29-2011 04:32 AM
You cannot use XCF32P the same way as describe in XAPP1100 because XCF32P doesn't have address bus.
For BPI, mode pins are sampled on the INIT rising_edge and so WBSTAR knows you are in BPI mode and goes to find the bitstream stored at the address you told. Each time, you erase the FPGA and do the same things as if you switch off and on your card (init, load, done).
For PR design with BPI memory, the FPGA is loaded with his own CCLK (because BPI is master mode and FPGA drive CCLK). Also, CCLK has a big tolerance on frequency(50% when generated by V5). If you do Multiboot before PR, put a logic analyzer on CCLK pin, you will see CCLK stops just after DONE goes high. It is a problem if you want to do PR because this will not sample datas on BPI bus. So, to avoid CCLK turned off, you have to activate SEU detection (go to see UG191) and implement FRAME_ECC in your design (in your constraint file, tell you do not want SEU detection on INIT pin). Do not forget to study memory timing for the BPI, you have "latency" for the first word of each page (do not forget bitgen options like for the Multiboot for BPI page size etc).
At the end, the reconfiguration time is better with BPI memory only because databus is twice larger than on XCF32P. But that's true, you have not to change the CPLD.
07-29-2011 04:52 AM
Wow, it is a lot more involved to reconfigure using multiboot than I originally thought. I see I still have a log way to go before being able to reconfigure. Thanks for pushing me into a new direction. I was trying to reconfigure using a similar way as described in XAPP1100, but (unsurprisingly) it didn't work.
I will give feedback as I progress. I anticipate that paper you are writing. Good luck with that. Hope you can get it published.
07-29-2011 05:20 AM
Like you, I began to try the same thing as told in Multiboot and I was facing many difficulties including what I wrote on the previous posts :)
For now it is not an easy way to achieve 100% hardware PR design but it is possible and it improves functionnality.
Hope you succeed for your PR design ;)
01-24-2012 10:20 AM
Iam trying to implement a PR with a FSM and ICAP. Now I can implement a Multiboot with full bitstream following the XAPP1100 but with partial bitstreams is not working. I also activated SEU detection but still is not working. I saw in another forum that lammonis was asking if the IPROG comand on the FSM colud be the problem. is it?
03-17-2012 02:04 PM
i am also working on a dynamic partial reconfiguration project,
can anyone help me about reconfiguration command and data sequence for ICAP primitive,
i find multiboot commands as you mentioned in application notes xapp1100, but partial reconfiguration commands are not so clear
any document content that commands would be very helpful
03-21-2012 06:56 AM
When you generate a PR bitstream, you can parse through it yourself (.bit or .rbt). The main difference you'll see is that not all config reg need to be set and your starting FAR and FDRI words can be different. In addition, you do not get GRESTORE in PR bitstream.
04-05-2012 08:20 AM
Alan and govemb, i think you are mixing 2 things.
For Multiboot, you must follows XAPP1100 and send the good commands (be careful about bitswapping) to do a correct Multiboot. You don't care about what ICAP does during full reconfiguration.
For PR, you must control and route signal to ICAP. Partial bitstream contains all ICAP need to do the partial reconfiguration. The main difficulty in fact is how to control de BPI. SEU detection is just to keep CCLK activ because BPI control signals are "clocked" on the CCLK even if it is in asynchronous mode.
I wrote a publication for the next Xcell journal (Q2 2012) about the hardware PR design with XCF32P. Perhaps you will find informations in it.
04-05-2012 08:26 AM
Good to hear form you again. Hope you are doing well. I'm looking forward to reading your publication in the next XCell journal.
11-04-2013 05:50 AM