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303 Views
Registered: ‎02-24-2019

Partial reconfiguration using VIVADO and zedboard

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Hi,

I am trying to implement an algorithm on zedboard using vivado 2018.3. Initially i just configured my FPGA and after verifying the results, i moved towards the partial reconfiguration. In my standard design, i used block designs. In partial reconfiguration project, i tried to declare a part of my code as PR, but when i use a block design (for AXI and IP packaging), it gives me errors. 

Secondly, i wanted to ask can i use netlist directly and declare it as PR module? 

Any answer would really be appreciated. 

_HF

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Moderator
Moderator
228 Views
Registered: ‎11-04-2010

Re: Partial reconfiguration using VIVADO and zedboard

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Hi, hunainafarid02@gmail.com ,

IP Integrator support is not in place. Block Diagrams cannot be included as RMs or
within RMs. Modules within Block Diagrams cannot be set as RMs.

Source types for Reconfigurable Modules: RTL, DCP, EDIF, XDC, XCI, XCIX.
 XCI or XCIX (Xilinx IP) cannot be the top level.
 EDIF cannot be a sub-module

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3 Replies
Xilinx Employee
Xilinx Employee
236 Views
Registered: ‎01-30-2019

Re: Partial reconfiguration using VIVADO and zedboard

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Moderator
Moderator
229 Views
Registered: ‎11-04-2010

Re: Partial reconfiguration using VIVADO and zedboard

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Hi, hunainafarid02@gmail.com ,

IP Integrator support is not in place. Block Diagrams cannot be included as RMs or
within RMs. Modules within Block Diagrams cannot be set as RMs.

Source types for Reconfigurable Modules: RTL, DCP, EDIF, XDC, XCI, XCIX.
 XCI or XCIX (Xilinx IP) cannot be the top level.
 EDIF cannot be a sub-module

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Don't forget to reply, kudo, and accept as solution.
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167 Views
Registered: ‎02-24-2019

Re: Partial reconfiguration using VIVADO and zedboard

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I figured out a way to do the partial reconfiguration. yes you were right, i could not do it with Block diagrams. I used the non project mode, and were able to generate the bit streams. Now i am facing another issue. I am getting garbage values on my terminal. for example, i have declared a one bit value in my program, and i should get either 1 or 0 on the terminal but instead i get 9DF39DF3. Also for data out i am getting 128 bits but not correct value. 
if i remove the partial reconfiguration from the same project, i get the correct values. but when i declare the project as partially reconfigurable, i get wrong values. Can you guide me where i am doing wrong?
P.S i am using AXI4 LITE interface. and SDK terminal for results. 

Waiting for response please.

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