cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
8,320 Views
Registered: ‎02-08-2013

Partitioning Tranciever Block

Jump to solution

Hello all,

 

I'm going through the hierachical design methodology guide (UG748) and I'm wondering if there is anything special I need to do, or if I am violating any rules with the following:

 

My heirarchical block contains a 10G PCS/ PMA core and MAC complete with tranceiver instantiation (GTE2 CHANNEL etc) and clock genration (156MHz) that I pass out and use in the rest of my design. 

 

How does treatment of clocks within the partition work? Would I need to add another clock constraint at the clk_out pin of the partition?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
14,240 Views
Registered: ‎04-16-2008

No, the design is processed just like a normal full design in terms of constraint propagation and timing analysis.  If you Partition contains GTE2 cells, you'll want to make sure that all dedicated logic (like the IBUFDS_GTE2) are in the partitioned module as well.

 

 

View solution in original post

2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
14,241 Views
Registered: ‎04-16-2008

No, the design is processed just like a normal full design in terms of constraint propagation and timing analysis.  If you Partition contains GTE2 cells, you'll want to make sure that all dedicated logic (like the IBUFDS_GTE2) are in the partitioned module as well.

 

 

View solution in original post

Highlighted
Adventurer
Adventurer
8,313 Views
Registered: ‎02-08-2013

Ah yea, they are. Cheers.

0 Kudos