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Observer jsammy
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927 Views
Registered: ‎09-19-2014

Per-RM constraints in Project Mode

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I am trying to migrate an existing Project-mode toolchain to a partial reconfig project, and I am having some interesting TCL/XDC issues that are causing me problems.

As part of my baseline non-PR toolchain I have some HDL-derived attributes that become net properties in Vivado.  After synthesis, I open the synthesized design and run some TCL commands to create extra timing requirements based on the nets that it finds.  Specifically, it is applying false path and max data delay requirements to all of these nets.

Now that I have moved some of my logic into an RM, I am no longer able to get these HDL-driven timing constraints to work.  I can use `open_run -pr_config config_2 synth_1` to open my synthesized design with my desired post-synthesis RM in place, and my TCL commands to poll the net seem to work, and I can even apply these constraints to a new constraint set.  But I cannot seem to get the config_2 implementation to use the new constraint set for its implementation, even though the Vivado gui shows it is use.  Is there something special that needs to be done to run each config with a different constraints set?  It seems like timing and implementation are always run with the constraint set from impl_1.

I am using Vivado 2017.4, if this has been fixed in a newer version I will gladly try that, but it will take me a while to update all of my IP.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

Re: Per-RM constraints in Project Mode

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This should be module (scoped) constraints, written as if the RM is the top-level. For more information on the suggested way to create constraints for PR designs, please reference the Managing Constraints for a PR Design section of the PR User Guide (ug909). This starts on page 79 of the 2018.2 version.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug909-vivado-partial-reconfiguration.pdf

 

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: Per-RM constraints in Project Mode

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Hi, @jsammy ,

If you intend to add XDC for other RM, you can add the these constraints with the source code of this RM in the same time in "Partial reconfiguration Wizard". 

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Observer jsammy
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Registered: ‎09-19-2014

Re: Per-RM constraints in Project Mode

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@hongh

Thank you for those details about including the XDC when the RM is created.

I have a follow-on question about this approach.

Should this XDC file include constraints with paths relative to the RM as a top-level, or should the paths be written for the RM implemented within the static design?

To be more specific, in my case the top-level static design includes the RM instantiated at `u_pl_subsystem/pdmd_pr_block.u_pdmd_pr`.  So which of the following is the appropriate constraint to use in an XDC file that is added via the "Partial Reconfiguration Wizard":

  1. set_max_delay -datapath_only -from [all_fanin -quiet -flat -start {u_pl_subsystem/pdmd_pr_block.u_pdmd_pr/u_ddrr/u_sym_mod/u_upconvertor/resampler_offset_async[0]}] -through [get_pins -of [get_nets {u_pl_subsystem/pdmd_pr_block.u_pdmd_pr/u_ddrr/u_sym_mod/u_upconvertor/resampler_offset_async[0]}]] -to [all_fanout -quiet -flat -end [all_fanin -quiet -flat -start {u_pl_subsystem/pdmd_pr_block.u_pdmd_pr/u_ddrr/u_sym_mod/u_upconvertor/resampler_offset_async[0]}]] 4.000
  2. set_max_delay -datapath_only -from [all_fanin -quiet -flat -start {u_ddrr/u_sym_mod/u_upconvertor/resampler_offset_async[0]}] -through [get_pins -of [get_nets {u_ddrr/u_sym_mod/u_upconvertor/resampler_offset_async[0]}]] -to [all_fanout -quiet -flat -end [all_fanin -quiet -flat -start {u_ddrr/u_sym_mod/u_upconvertor/resampler_offset_async[0]}]] 4.000

Thanks for your help.

Jae

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

Re: Per-RM constraints in Project Mode

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This should be module (scoped) constraints, written as if the RM is the top-level. For more information on the suggested way to create constraints for PR designs, please reference the Managing Constraints for a PR Design section of the PR User Guide (ug909). This starts on page 79 of the 2018.2 version.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug909-vivado-partial-reconfiguration.pdf

 

Observer jsammy
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Registered: ‎09-19-2014

Re: Per-RM constraints in Project Mode

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Wonderful, thanks for the pointer.  I'll more closely read the documentation.

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Observer jsammy
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Registered: ‎09-19-2014

Re: Per-RM constraints in Project Mode

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@woodsd

In my RM design, I have exported the synthesized netlist as both .edn and .v, and also exported the constraints including my custom per-RM constraints.  In my PR project, when I add my RM to the project I can include the .v and .xdc files, but the timing constraints within the .xdc file do not appear to be used by implementation (i.e. my set_false_path and set_max_delay paths are still showing up as failing timing in my implemented sub-config).  When I select my RM in the "Partition Definitions" list, I can see both the .v and .xdc files, and the .xdc file says it is used in both synthesis and implementation.  I then tried adding the .edn file, but it does not seem to let me include the .xdc when I include my RM as an .edn file.

Could this be something to do with my version?  I am on 2017.4, and I see the latest is 2018.2.

Thanks for any help you can provide.

-Jae

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