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codewarrior1241
Observer
Observer
10,685 Views
Registered: ‎07-11-2010

PlanAhead and PCIe Endpoint Clocking

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Hi All,

 

I'm using a Spartan-6 150T, and am having trouble setting up PCIe endpoint clocking... I have a 1-lane PCIe implementation, and am usinging the X0Y1 transceiver, which I selected in CoreGen. I have placed the Tx and Rx pins on the GTPA, but can't place the differential clock sys_clk! PlanAhead keeps telling me that the A10 and B10 pins on the GTPA - MGTREFCLK0P and N - are not global clock pins, and sys_clk is a global clock.

 

However, in my design, I have sys_clk going into a IBUFDS primitive like so:

 

refclk_ibuf : IBUFDS
port map
(
    O  => sys_clk_c,
    I  => sys_clk_p,
    IB => sys_clk_n
);

This was recommended in the PCIe User's Guide... IBUFDS are not global clock buffers, right? Hence, why would PlanAhead consider them global clocks? Else, how can I tell PlanAhead that this is NOT a global clock, and have it let me place the pins on the GTPA? If I don't, and put sys_clk on global clock pins elsewhere, the design fails in MAP.

 

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codewarrior1241
Observer
Observer
17,287 Views
Registered: ‎07-11-2010

As I said above, the error WAS that I couldn't actually place PCIe clock port on the appropriate pins of the GTP.

 

I had figured this out though - I had a circuit that used inputted the differential signals of the PCIe clock and ran them through a IBUFDS which should be OK, and the subsequent signal clocked some of my logic, which was not OK. This forced PlanAhead to believe that the PCIe clock was actually a global clock (since that what my logic was using), and it would only let me place it on a global clock pin, not a GTP pin. When I got rid of that clock from the process sensitivity list of my logic, and replaced it with a different, known-external clock, things placed fine, and the design routed and worked.

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Anonymous
Not applicable
10,613 Views

What is the error you are getting from planAhead?

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codewarrior1241
Observer
Observer
17,288 Views
Registered: ‎07-11-2010

As I said above, the error WAS that I couldn't actually place PCIe clock port on the appropriate pins of the GTP.

 

I had figured this out though - I had a circuit that used inputted the differential signals of the PCIe clock and ran them through a IBUFDS which should be OK, and the subsequent signal clocked some of my logic, which was not OK. This forced PlanAhead to believe that the PCIe clock was actually a global clock (since that what my logic was using), and it would only let me place it on a global clock pin, not a GTP pin. When I got rid of that clock from the process sensitivity list of my logic, and replaced it with a different, known-external clock, things placed fine, and the design routed and worked.

View solution in original post

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