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Visitor shrek
Visitor
15,006 Views
Registered: ‎10-27-2009

Problem in partial reconfiguration!

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Hi all,

 

Now I'm working on the parital reconfiguration project. There are two data paths in my design and just one of them can be reconfigured when the other one is running.  And the output of the two data paths should be merged to one output at the output port(I design a FSM to control the output merge). I followed the PR design guide and finished all the design flows and generated the full bitstream and partial bitstream. When downloading the full bitstream, the FPGA runs well. However, when starting to partially configure one data path, the outputs are error. Does anyone know what happened? Please let me know. Thank you.

 

By the way, I have tried some experiments on partial reconfiguration and successed. But they did not refer to the data path, just some control elements in the design.

 

Regards,

Dong

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Scholar austin
Scholar
21,364 Views
Registered: ‎02-27-2008

Re: Problem in partial reconfiguration!

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s,

 

A simple difference between bit streams without floorplanning, and being aware of the connections, will likely behave as you have found.


Why?

 

The "new" partial bitstream not only programs the new functionality, but it also "deletes" the old functionality.

 

If the reconfigured portion is not constrained to a specific fixed area, with specific fixed ports, pretty much anything can happen (while reconfiguring).

 

Imagine a net with a source, and two destinations :  if you rip up the middle of this net to add a new destination, you break the path to the other destination.

 

The old flow:

 

http://www.xilinx.com/support/documentation/application_notes/xapp290.pdf

 

Is very simple, and can not really accomplish a great deal, just for the reasons detailed above.  It is good for changing IO standards, LUT conents, etc. but not well suited to replaceable IP blocks being exchanged.

 

The present recommended PR flow uses PlanAhead to place the element to be reconfigured into a region, and both the first bitstream, and the subsequent partial bitstream (and the third 'go back to the first' functionality bitstream) all affect the logic only within that region.

 

Now, if you rip up the path to the destination within the region, it gets replaced with a new path to the new destination, without breaking the 'other' destination...

 

I am simplifying this quite a bit, there are also "bus macros" that allow these connections to remain unaffected while reconfiguring, example:

 

http://gregorymermoud.ch/wp-content/uploads/dprtutorial.pdf

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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7 Replies
Scholar austin
Scholar
21,365 Views
Registered: ‎02-27-2008

Re: Problem in partial reconfiguration!

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s,

 

A simple difference between bit streams without floorplanning, and being aware of the connections, will likely behave as you have found.


Why?

 

The "new" partial bitstream not only programs the new functionality, but it also "deletes" the old functionality.

 

If the reconfigured portion is not constrained to a specific fixed area, with specific fixed ports, pretty much anything can happen (while reconfiguring).

 

Imagine a net with a source, and two destinations :  if you rip up the middle of this net to add a new destination, you break the path to the other destination.

 

The old flow:

 

http://www.xilinx.com/support/documentation/application_notes/xapp290.pdf

 

Is very simple, and can not really accomplish a great deal, just for the reasons detailed above.  It is good for changing IO standards, LUT conents, etc. but not well suited to replaceable IP blocks being exchanged.

 

The present recommended PR flow uses PlanAhead to place the element to be reconfigured into a region, and both the first bitstream, and the subsequent partial bitstream (and the third 'go back to the first' functionality bitstream) all affect the logic only within that region.

 

Now, if you rip up the path to the destination within the region, it gets replaced with a new path to the new destination, without breaking the 'other' destination...

 

I am simplifying this quite a bit, there are also "bus macros" that allow these connections to remain unaffected while reconfiguring, example:

 

http://gregorymermoud.ch/wp-content/uploads/dprtutorial.pdf

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor shrek
Visitor
14,991 Views
Registered: ‎10-27-2009

Re: Problem in partial reconfiguration!

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Hi Austin,

 

Thanks for your reply.  I can understand what you refered.  You're right that during partial reconfiguration the old modular in the reconfigurable area is deleted and reconfigured with the new one. However, in my design, some importance as mentioned in the  http://gregorymermoud.ch/wp-content/uploads/dprtutorial.pdf maybe not directly help me to figure out my problems.  I applied the EAPR for partial reconfiguration in Xilinx II Pro 50 1152-7  FPGA chip and download the bit stream through JTAG.  My Xilinx tools are ISE 9.2i (sp4) + EAPR + planahead10.1.   Some problems that confuse me are the bus macro and the placement of RP area. I used the bus macro between the RP area and static area, which is downloaded from Xilinx official website. The RP area is placed from (X:9, Y:7) to (X:25, Y:32) and all the bus macro are Right-to-Left. And I have totally used 20 bus macros between RP and static area. There are two data paths.  One is running in static area and one runs in RP area. The merge modular also runs in static area and merges the two data paths in round robin way. I generated two RP bit streams with only one difference to show RP completion. Errors happened during RP, and all outputs are equal to logic "1", while the input of the RP modular from static area seems running well. The FSM in merge modular is out of control at that moment. There is no error message during RP design flow(I followed by the guide from Xilinx web: Earky Access Partial REconfiguration User Guide for ISE 9.2.04i). 

 

I have done some samples in such design flow, and I successed. When I enlarged the RP area and added some bus macro for new design, errors happened.

 

Could you please show me some details about the bus macro(type, placement, requirment) and contraints on the RP area placement in Virtex II Pro 50 ? Thank you very much.

 

By the way,  my email is yindon1982@gmail.com. 

 

Regards,

Dong

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Scholar austin
Scholar
14,979 Views
Registered: ‎02-27-2008

Re: Problem in partial reconfiguration!

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s,


I just hit my limits of expertise.


Perhaps someone else can help.


Clearly you understand the issues, and also, clearly, it isn't working without a glitch.


Have you tried examining the (different complete) bitstreams in FPGA_editor?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor shrek
Visitor
14,943 Views
Registered: ‎10-27-2009

Re: Problem in partial reconfiguration!

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Great sugguestion. I am checking now!
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Visitor shrek
Visitor
14,855 Views
Registered: ‎10-27-2009

Re: Problem in partial reconfiguration!

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Hi Austin,

 

I have checked the floorplan by ISE FPGA Editor. When I check the sample that ran well in PR process, I found that few signals from static region go across the PR region straightly to another static region. (I just used the orignial constraint file and modified it by PlanAhead) when it came to my large PR region design, I found lots of signals from static region  go through PR region circuitously. I used EAPR method for PR, so I haven't used FPGA editor for PR before. I wonder whether the situation that I met is correct or not? Thank you. By the way, my email address is : dyin@engin.umass.edu or yindong1982@gmail.com. I think gmail is better for me. Shall we contact through email? Thanks again.

 

Cheers,

Dong

 

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Scholar austin
Scholar
14,852 Views
Registered: ‎02-27-2008

Re: Problem in partial reconfiguration!

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OK,

 

So now you see why it breaks when it gets reconfigured.  I do not know the solution to this, other than to re-arrange the physical placement, so the signals in question do not get routed this way.  I know there are placement constraints that you can add, and even "keep out" constraints that can be specified, but that is well beyond my knowledge.  Perhaps by re-arranging the block outlines in PlanAhead, you can also accomplish waht you require?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor bhuvaneswari
Visitor
12,070 Views
Registered: ‎03-12-2013

Re: Problem in partial reconfiguration!

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hiii Mr.Dong...im bhuvaneswari...i read ur messages ...im doing a project on partial reconfiguration using eapr design
flow....i just have selected the project and about to start it....im having virtex 2 pro fpga board....and i want to know can this project be done on the virtex2 pro  board....i have read ur messages that u have done this project and successed in various steps....can you give me any suggestions regarding the project......im a starter...even i dnt know how to deal with
the FPGA board.....or else please send me if u have any documents or any sample codings that u have used in your project...so that it will be helpful to me.....im not familiar with how i have to start my project.....please do help me....i will be very thankful to u..

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