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kmzac1993
Newbie
Newbie
3,472 Views
Registered: ‎03-03-2019

Problem initializing memory in Verilog

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I am trying to initilize the first 5 locations of a memory in verilog. The design works for smaller depth, but for 32 bit address it will only initialize the first element. 

I get the following warning for index 1 - 4:  select index 1 into 'mem' is out of bounds 

module DM #(parameter WL = 32, ADDRW = 32)
(input RST,
input [ADDRW-1:0] ADDR,
output [WL-1:0] DMRD);

reg [WL-1:0] mem [2**ADDRW-1:0]; 


always @ (posedge RST) begin
if (RST) begin
 mem [0] <= 32'h00000011;
 mem [1] <= 32'h0000001f;
 mem [2] <= 32'hfffffffb;
 mem [3] <= 32'hfffffffe;

 mem [4] <= 32'h000000fa;
end
end

assign DMRD = mem [ADDR];

endmodule

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markcurry
Scholar
Scholar
3,261 Views
Registered: ‎09-16-2009

I suggest first reviewing the "RAM HDL Coding Techniques" section of The Vivado Synthesis User Guide (UG901).  This will help you correctly impllement a large memory such that the Vivado toolset can properly manage your code.

Second, please consider what you're asking for:

reg [WL-1:0] mem [2**ADDRW-1:0]; 

With both "WL",and "ADDRW" set to 32 as your header requests as defaults, you're asking the tool for 32x(2**32)  = 128 Gigabits of memory cells.  That's huge, and no FPGA (nor any FPGA that will be on the market for many years) will have that kind of memory on it.

I can perhaps guess, that the error you're getting may be that the tool is just running out of memory.  A better error message would be helpful, but it's definetly a possible answer for the error you are seeing.

Regards,

Mark

 

 

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3 Replies
drjohnsmith
Teacher
Teacher
3,421 Views
Registered: ‎07-09-2009
ignoring the verilog
how are you expecting this to work in the FPGA ?
memories can not be initialised to arbitrary values with a signal, so this would have to be made in LUT based registers,

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dror_m
Observer
Observer
3,415 Views
Registered: ‎06-19-2019
memories does not have resets. you can create memory that is based on regs (and have reset) as drjohnsmith mentioned, but this is basically good for small scale memories.
so you need to think whether you need reset? if you need just one time initialization, so this is doable and the value will be written when the bit is loaded. if u must!!! have memory that u can reset, then use register based RAM.
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markcurry
Scholar
Scholar
3,262 Views
Registered: ‎09-16-2009

I suggest first reviewing the "RAM HDL Coding Techniques" section of The Vivado Synthesis User Guide (UG901).  This will help you correctly impllement a large memory such that the Vivado toolset can properly manage your code.

Second, please consider what you're asking for:

reg [WL-1:0] mem [2**ADDRW-1:0]; 

With both "WL",and "ADDRW" set to 32 as your header requests as defaults, you're asking the tool for 32x(2**32)  = 128 Gigabits of memory cells.  That's huge, and no FPGA (nor any FPGA that will be on the market for many years) will have that kind of memory on it.

I can perhaps guess, that the error you're getting may be that the tool is just running out of memory.  A better error message would be helpful, but it's definetly a possible answer for the error you are seeing.

Regards,

Mark

 

 

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