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Visitor frnfern
Visitor
793 Views
Registered: ‎11-22-2017

Problem with Make NetFPGA 10G

Hi everyone, 

 

I'm using Virtex5 TXT and trying to use 'make' to compile NetFPGA-10G-live.git

Here are the error that I found.

 

[root@172 NetFPGA-10G-live]# make

for lib in  axi_emc_v1_01_a axi_gpio_v1_01_a axi_interconnect_v1_02_a axi_timebase_wdt_v1_01_a axi_uartlite_v1_01_a bram_block_v1_00_a 
clock_generator_v4_01_a diff_input_buf_v1_00_a lmb_bram_if_cntlr_v2_10_b lmb_v10_v1_00_a microblaze_v8_00_b proc_common_v3_00_a 
proc_sys_reset_v3_00_a ; do \

    if test -f lib/hw/xilinx/pcores/$lib/Makefile; \

        then make -C lib/hw/xilinx/pcores/$lib; \

    fi; \

done;

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/axi_emc_v1_01_a'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_emc_v1_01_a/* . > /dev/null 2>&1

make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/axi_emc_v1_01_a'

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/axi_gpio_v1_01_a'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/* . > /dev/null 2>&1

make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/axi_gpio_v1_01_a'

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/axi_interconnect_v1_02_a'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/* . > /dev/null 2>&1

make[1]: *** [install] Error 1
make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/axi_interconnect_v1_02_a'

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/axi_timebase_wdt_v1_01_a'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timebase_wdt_v1_01_a/* . > /dev/null 2>&1

make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/axi_timebase_wdt_v1_01_a'

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/axi_uartlite_v1_01_a'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/* . > /dev/null 2>&1

make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/axi_uartlite_v1_01_a'

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/bram_block_v1_00_a'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/* . > /dev/null 2>&1

make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/bram_block_v1_00_a'

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/clock_generator_v4_01_a'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/* . > /dev/null 2>&1

make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/clock_generator_v4_01_a'

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/lmb_bram_if_cntlr_v2_10_b'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_b/* . > /dev/null 2>&1

make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/lmb_bram_if_cntlr_v2_10_b'

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/lmb_v10_v1_00_a'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/* . > /dev/null 2>&1

make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/lmb_v10_v1_00_a'

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/microblaze_v8_00_b'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_00_b/* . > /dev/null 2>&1

make[1]: *** [install] Error 1
make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/microblaze_v8_00_b'

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/proc_common_v3_00_a'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/* . > /dev/null 2>&1

make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/proc_common_v3_00_a'

make[1]: Entering directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/proc_sys_reset_v3_00_a'

false | cp -ri /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/* . > /dev/null 2>&1

make[1]: Leaving directory `/home/ajanvara/project/NetFPGA-10G-live/lib/hw/xilinx/pcores/proc_sys_reset_v3_00_a'

/////////////////////////////////////////
//Xilinx EDK cores installed.
/////////////////////////////////////////

Any idea to solve these problem ?

Thanks

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1 Reply
Moderator
Moderator
727 Views
Registered: ‎02-07-2008

Re: Problem with Make NetFPGA 10G

@frnfern, I would suggest redirecting the question to the the NetFPGA team. Also, try using ISE 13.4, the version that was used to create NetFPGA-10G.

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