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Observer ertugrul
Observer
15,875 Views
Registered: ‎10-08-2009

Question: Planahead guard regions?

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Hello

 

I am using planahead 10.1 and I want use some guard regions in my floorplan; meaning that neither implemetation nor routing will be done at that regions. Is it possible to define such regions in planahead 10.1 such that no implementation nor routing will be done at that regions in short this areas will be totaly free

thanx

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Xilinx Employee
Xilinx Employee
23,137 Views
Registered: ‎08-13-2007

Re: Question: Planahead guard regions?

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Most applications do not require guard regions - but some do.

 

The PR (partial reconfiguration) flow would be used here. ISE 10.1 does not support PR. Virtex-II also wouldn't be my first choice here.

 

Some background,

http://forums.xilinx.com/xlnx/board/message?board.id=IMPBD&message.id=696 (ML510 - Partial Reconfiguration)

 

I would discuss your requirements with a Xilinx FAE to decide how/if you can proceed. This capability exists but is not generally deployed currently in the general customer base. You'll want to discuss your application in more detail. This forum is likely not the ideal mechanism for that support.

 

bt

 

9 Replies
Xilinx Employee
Xilinx Employee
15,861 Views
Registered: ‎08-13-2007

Re: Question: Planahead guard regions?

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The short answer is yes it is possible in some situations. But there are other considerations (including SW version, device family, tool flow, constraints, etc.)

In general, the details are not publicly documented in an unrestricted manner.

 

Why do you want to do this?

 

bt

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Observer ertugrul
Observer
15,846 Views
Registered: ‎10-08-2009

Re: Question: Planahead guard regions?

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Hello,

 

I am using ISE 10.1 with service pack 3 + planahead 10.1.8 and I want to implement this guard regions in virtex2-fg456-4. I want to use this regions because I want to seperate my circuits to prevent  signal interference from one to other. Now is it possible for me to implement this regions and how? If it is not possible doing it in virtex2 I can change FPGA.

 

thanks in advance

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Xilinx Employee
Xilinx Employee
23,138 Views
Registered: ‎08-13-2007

Re: Question: Planahead guard regions?

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Most applications do not require guard regions - but some do.

 

The PR (partial reconfiguration) flow would be used here. ISE 10.1 does not support PR. Virtex-II also wouldn't be my first choice here.

 

Some background,

http://forums.xilinx.com/xlnx/board/message?board.id=IMPBD&message.id=696 (ML510 - Partial Reconfiguration)

 

I would discuss your requirements with a Xilinx FAE to decide how/if you can proceed. This capability exists but is not generally deployed currently in the general customer base. You'll want to discuss your application in more detail. This forum is likely not the ideal mechanism for that support.

 

bt

 

Observer ertugrul
Observer
15,825 Views
Registered: ‎10-08-2009

Re: Question: Planahead guard regions?

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Even if I get access or not to that lounge there is a reality about that I have to change my ISE version from 10.1 to 11 to perform PR. Am I right?
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Observer ertugrul
Observer
15,823 Views
Registered: ‎10-08-2009

Re: Question: Planahead guard regions?

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what is the latest version that supports PR before ISE 11?
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Xilinx Employee
Xilinx Employee
15,821 Views
Registered: ‎08-13-2007

Re: Question: Planahead guard regions?

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Maybe - you couldn't use 10 - you may also be able to go back to 9 depending on the family.

 

9.2.04PR12 (service pack 4 with PR overlay 12) is the last version before 10 that supported PR.

 

Note also that ISE 11:

-requires a special PR license

-does not support several of the older Virtex families (V, V-E, V-II, and V-II Pro)

-first supported V6/S6 publicly in 11.2

There are also differences in the tool support when a family is first supported for general usage and if/when/how it is supported for PR.

 

bt

 

As I've said other places - PR is an intensive flow. These are the easy questions... ;)
 

 

 

Message Edited by timpe on 12-23-2009 06:29 PM
Observer ertugrul
Observer
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Registered: ‎10-08-2009

Re: Question: Planahead guard regions?

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Hello timpe,

thanx for your help but this sentece is taken from PR user guide:

 

"PlanAhead PR functionality will continue to evolve in subsequent 10.1.x releases..."  what does this sentence mean? Do I understand wrong? I have planahead 10.1.8 and I can not do PR. Why did they put this sentence into user guide. Am I wrong or missing something. Where am I wrong

 

thank you

Message Edited by ertugrul on 12-23-2009 03:36 PM
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Xilinx Employee
Xilinx Employee
15,806 Views
Registered: ‎08-13-2007

Re: Question: Planahead guard regions?

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You have the benefit of hind-sight... The author of that user guide did not.

 

The short story is PR was redesigned to go from a modular-based flow to a partition-based flow (an example of major parts of its evolution). Coupled with the status of tool depencies, engineering resources, etc. - it was not supported in 10.1. It was brought back in 11 with a number of important differences. There ended up being a number of reasons why it wasn't practical to support PR in 10 like was originally planned.

 

So it did evolve - just in a different way that some might have expected.

 

bt

 

 

 

Xilinx Employee
Xilinx Employee
15,804 Views
Registered: ‎08-13-2007

Re: Question: Planahead guard regions?

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It should also be noted that PA 10.1.8 does support PR. But ISE 10 does not. For example, PA 10.1.8 can be used with ISE 9.2.04PR12.

 

PA and ISE used to be fairly decoupled but that too has changed over time. I would expect users of PR in 11 to use the same version of PA and ISE. But it didn't always used to be that way.

 

bt

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