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Registered: ‎06-14-2018

Question about different memories inside PCIe FPGA (Alveo)

Hi,

i'm designing a naive little graph representing the memories inside an Alveo.

As it's not rigorous, I would like some advice for a redesign.

What would be correct to link inside the right block, e.g. can a flip-flop be directly linked to the global RAM etc. ?

fpga-pcie-archi-ram.png
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