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Scholar pumaju1808
Scholar
2,675 Views
Registered: ‎08-14-2007

RTL-FPGA designs in system generator?

Hi,

 

I have an RTL design which we do modification in order to have it in the FPGA, my question is about once I have my FPGA code of my system is it possible to export that into a system generator (SG) ambient? Something like from Verilog --> SG, I know there is a black box where you can import your code, however I'm talking about a much bigger design

 

the idea is to have a kind of simulation of the system with fpga resources in system generator

 

I'd like to ear your inputs

 

 

 

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2 Replies
Moderator
Moderator
2,622 Views
Registered: ‎09-15-2016

Re: RTL-FPGA designs in system generator?

Hi @pumaju1808,

 

Check if this helps: https://www.xilinx.com/video/hardware/vivado-hls-block-system-generator-dsp.html

 

Regards,
Prathik
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Scholar pumaju1808
Scholar
2,579 Views
Registered: ‎08-14-2007

Re: RTL-FPGA designs in system generator?

Thanks prathikm, this is useful
Let me ask another question:
Is there any file (human readable) that has information of the schematic representation of my design?. For example, when you have a shematic representation in Vivado, I assume this information is read from some file, where this file have all the information of the cells and their interconnection, is it possible to have access to this file?

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