Replace DDR4 SDRAM MIG IP memory part without re-running synthesis+implementation

[dpayet]

I have a base design, from which I create 2 flavors (say A and B).

FlavorA : uses DDR4 SDRAM MIG IP with 1G memory part 

FlavorB : uses DDR4 SDRAM MIG IP with 512M memory part 

For ease of design/timing closure, I would like to do ONE synthesis+implementation, say addressing Flavor-A.

Then, I would like to replace the FlavorA/MIG with FlavorB/MIG, redo some minor connections, and do a very limited incremental build.

Is this feasible?

Any suggestions on the methodology -- 

It will greatly help us with timing closure and runtime.

[hongh]

You can consider the NFX flow described in UG909 with DDR module as dynamic logic.

[dpayet]

Could you mention the chapter/section you are referring to? I was not able to find the NFX flow in UG909

[marcb]

Hi @dpayet The acronym is DFX or Dynamic Function eXchange which was previously known as Partial Reconfiguration. The entire contents of UG909 cover this flow. The name has changed recently (2019.2) in the documentation.