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473 Views
Registered: ‎02-17-2020

Ring oscillator design

Hi all,

 I wrote verilog code for Ring oscillator.  I want to implement Ring oscillator in Vivado. I have doubts like how to include delays for oscillator. How to monitor the results and so. Can anyone help me in this regard.

 

 

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6 Replies
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Contributor
Contributor
380 Views
Registered: ‎10-25-2019

Re: Ring oscillator design

Can you share your code so that we can show how delays are added and calculated? 

Regards,
jagannath@logictronix.com
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Teacher
Teacher
365 Views
Registered: ‎07-09-2009

Re: Ring oscillator design

Have you searched the forums / web,

   this is a very popular topic, especialy among prof's / students,

The basic problem your going to find, is your fighting the tools,

     The tools are designed to minimise the delays / simplify the design, 

       so a ring oscillator of say 11 inverters, will be "optimised" to a single inverter.

 

two basic ways, these should give you pointers.

https://forums.xilinx.com/t5/Other-FPGA-Architecture/How-to-implement-a-ring-oscillator-with-routings-of-FPGA-Where/td-p/768444

and

https://www.xilinx.com/support/documentation/application_notes/xapp872.pdf

 

 

 

 

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349 Views
Registered: ‎02-17-2020

Re: Ring oscillator design

Thank you sir. Information you gave is useful. I wanted to know how to include delay elements in the verilog code. To check the simulation results sir.

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344 Views
Registered: ‎02-17-2020

Re: Ring oscillator design

module Single_bit(input en,
input s0,
input s1,
input s2,
output out1,
output out2,
output out3,
output out4,
output out5,
output out6,
output out7,
output out8,
output y1,
output y2,
output reg [7:0]count1,
output reg [7:0]count2,
output reg bout
//output reg [7:0]HD,
//output reg [7:0]xorval
);
wire o_y1,o_y2;
(* S= "TRUE"*)(* ALLOW_COMBINATORIAL_LOOPS = "true", KEEP = "true" *)
// wire wout1,wout2,wout3,wout4,wout5,wout6,wout7,wout8;
//wire wout1_1,wout1_2,wout1_3,wout1_4,wout1_5,wout1_6,wout1_7,wout1_8;

wire w11, w12, w13,w14,w15,w16,w17,w18,w19,w20,w21;
wire w2_1, w2_2, w2_3,w2_4,w2_5;
wire w3_1, w3_2, w3_3,w3_4,w3_5;
wire w4_1, w4_2, w4_3,w4_4,w4_5;
wire w5_1, w5_2, w5_3,w5_4,w5_5;
wire w6_1, w6_2, w6_3,w6_4,w6_5;
wire w7_1, w7_2, w7_3,w7_4,w7_5;
wire w8_1, w8_2, w8_3,w8_4,w8_5;

wire w211, w212, w213,w214,w215,w216,w217,w218,w219,w220,w221;
wire w22_1, w22_2, w22_3,w22_4,w22_5;
wire w23_1, w23_2, w23_3,w23_4,w23_5;
wire w24_1, w24_2, w24_3,w24_4,w24_5;
wire w25_1, w25_2, w25_3,w25_4,w25_5;
wire w26_1, w26_2, w26_3,w26_4,w26_5;
wire w27_1, w27_2, w27_3,w27_4,w27_5;
wire w28_1, w28_2, w28_3,w28_4,w28_5;



wire w1,w2,w3,w4,w5,w6,w7,w8;
wire w1_1,w1_2,w1_3,w1_4,w1_5,w1_6,w1_7,w1_8;


integer i;
initial count1 = 8'd0;
initial count2 = 8'd0;
initial bout = 0;
reg [31:0]rand_no_full;
/*
initial begin
assign rand_no_full=$random();
set1=rand_no_full[3:0];
set2=rand_no_full[7:4];
set3=rand_no_full[11:8];
set4=rand_no_full[15:12];
set5=rand_no_full[19:16];
set6=rand_no_full[23:20];
set7=rand_no_full[27:24];
set8=rand_no_full[31:28];
end
*/

and #1(w11, en, out1);
not #1(w12, w11);
not #1(w13, w12);
not #1(w14,w13);
not #1(w15, w14);
not #1(out1, w15);

and #2(w2_1, en, out2);
not #2(w2_2, w2_1);
not #2(w2_3, w2_2);
not #2(w2_4,w2_3);
not #2(w2_5, w2_4);
not #2(out2, w2_5);

and #3(w3_1, en, out3);
not #2(w3_2, w3_1);
not #3(w3_3, w3_2);
not #2(w3_4,w3_3);
not #3(w3_5, w3_4);
not #2(out3, w3_5);

and #4(w4_1, en, out4);
not #2(w4_2, w4_1);
not #4(w4_3, w4_2);
not #2(w4_4,w4_3);
not #4(w4_5, w4_4);
not #4(out4, w4_5);

and #2(w5_1, en, out5);
not #5(w5_2, w5_1);
not #5(w5_3, w5_2);
not #2(w5_4,w5_3);
not #5(w5_5, w5_4);
not #5(out5, w5_5);

and #6(w6_1, en, out6);
not #2(w6_2, w6_1);
not #6(w6_3, w6_2);
not #2(w6_4,w6_3);
not #6(w6_5, w6_4);
not #6(out6, w6_5);

and #2(w7_1, en, out7);
not #7(w7_2, w7_1);
not #7(w7_3, w7_2);
not #7(w7_4,w7_3);
not #2(w7_5, w7_4);
not #7(out7, w7_5);

and #8(w8_1, en, out8);
not #8(w8_2, w8_1);
not #2(w8_3, w8_2);
not #8(w8_4,w8_3);
not #8(w8_5, w8_4);
not #2(out8, w8_5);



assign w1=(~s0)&(~s1)&out1;
assign w2=(~s0)&s1&out2;
assign w3=s0&(~s1)&out3;
assign w4=s0&s1&out4;
assign y1=w1|w2|w3|w4;


assign w5=(~s0)&(~s1)&out5;
assign w6=(~s0)&s1&out6;
assign w7=s0&(~s1)&out7;
assign w8=s0&s1&out8;
assign y2=w5|w6|w7|w8;

always @(posedge y1)
begin
count1<=count1+1;
end

always @(posedge y2)
begin
count2<=count2+1;
end

initial begin
#1000;
if(count1>=count2)begin
bout=1;
end
else begin
bout=0;
end


end

endmodule

Highlighted
342 Views
Registered: ‎02-17-2020

Re: Ring oscillator design

Sir,

I have given my code. I have added delay using # construct. If i try using $ random function, for two bits it's working and for the third bit, it gives error like, iteration limit is reached. Possible zero delay oscillation.

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Highlighted
Teacher
Teacher
212 Views
Registered: ‎07-09-2009

Re: Ring oscillator design

the # construct only works in simulation, not in the real chip
and your code will be optimised away to a single gate as you have none of the lock or other constraints mentioned in the app notes.
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