12-19-2015 10:35 AM
Is there any information from Xilinx about internal structue of routing switch boxes, on any FPGA generation? During manual routing I found out that by clicking on a switch-box pin, all possible routings are shown, but I am curious to see if there is any document about it.
12-19-2015 11:01 AM - edited 12-19-2015 11:05 AM
For manual placement and routing please go through the following links:
http://www.xilinx.com/support/sw_manuals/2_1i/download/fpedit.pdf (chapter#3 42 page onwards switch box(chapter#3-44))
12-19-2015 11:16 AM
Actually I know how to do manual routing, I am just curious about structure of switch box, I already know there are few different popular architectures ( wilton, disjoint,...)...
is there any published information about this from xilinx?
10-13-2017 12:02 PM