UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor sungh
Visitor
250 Views
Registered: ‎07-05-2019

SDK error when PS communicated with PL through AXI lite

Now i am using vivado for program development. Our team members use both Vivado HLS and Verilog. All the modules coding by HLS and Verilog need to communicate with PS. we use the AXI Lite interface. Now we're going to integrate the modules into one project and start to debug the SDK program.Then the problem comes. The driver files generated by HLS  and Verilog are different. When we try to put the driver files together there are some errors.  But when we test the Verilog and HLS modules  seperately with the seperate driver file they generated, the PS and PL can communicated well through the AXI Lite interface. So my questions is, can both of these two different develop language work together in SDK? the driver files are the .h and .c files. Has anyone ever had a similar problem? Does SDK support this way of working? Thanks!

Tags (3)
0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
159 Views
Registered: ‎07-11-2019

Re: SDK error when PS communicated with PL through AXI lite

Hello @sungh 

I will redirect you to a past forum article that I believe will help! What I believe will work is that you would export the HLS ip into your IP catalog that you can access through IP Integrator in vivado. Create your block design with your RTL and HLS IP. Then, you would run synthesis and implementation like normal and generate a bitstream. Lastly, export that bitstream and launch SDK and start your SDK flow. 

I have also attached an answer record and UG that I believe will help in exporting your HLS IP! 

Forum: https://forums.xilinx.com/t5/Design-Entry/Import-packaged-HLS-IP-into-Vivado-IP-catalog/td-p/785468

AR: https://www.xilinx.com/support/answers/60927.html

UG902: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug902-vivado-high-level-synthesis.pdf (for reference)

I hope this helps! 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

0 Kudos