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Visitor
Visitor
311 Views
Registered: ‎02-11-2020

SIMD Architecture

Dear Sir/Madam,


I want to implement SIMD architecture on FPGA. I am new in this field and try finding a software for simulating and implementing SIMD architecture. Can you please guide me about this? I really appreciate your help.

Kind Regards
Firas

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Scholar
Scholar
215 Views
Registered: ‎09-16-2009

Re: SIMD Architecture

A simple adder/subtractor in SystemVerilog:

module adder_sub
#( 
  parameter WORD_SIZE = 8
) ( input wire clk_i, input wire add_sub_i, input wire [ WORD_SIZE - 1 : 0 ] a_i, input wire [ WORD_SIZE - 1 : 0 ] b_i, output wire [ WORD_SIZE - 1 : 0 ] y_o ); bit [ WORD_SIZE - 1 : 0 ] y; always @( posedge clk_i ) if( add_sub_i ) // subtract == 1 y <= a_i - b_i; else y <= a_i + b_i; assign y_o = y; endmodule

Now the same design, modified to be SIMD:

 

module adder_sub_simd
#( 
  parameter WORD_SIZE = 8,
  parameter NUM_ALU = 4
)
(
  input  wire clk_i,
  input  wire add_sub_i,
  input  wire [ NUM_ALU - 1 : 0 ][ WORD_SIZE - 1 : 0 ] a_i,
  input  wire [ NUM_ALU - 1 : 0 ][ WORD_SIZE - 1 : 0 ] b_i,
  output wire [ NUM_ALU - 1 : 0 ][ WORD_SIZE - 1 : 0 ] y_o
);

bit [ NUM_ALU - 1 : 0 ][ WORD_SIZE - 1 : 0 ] y;
generate
  for( genvar j = 0; j < NUM_ALU; j++ )
  begin : iter_alu
    always @( posedge clk_i )
      if( add_sub_i ) // subtract == 1
        y[ j ] <= a_i[ j ] - b_i[ j ];
      else
        y[ j ] <= a_i[ j ] + b_i[ j ];
end
endgenerate
assign y_o = y; endmodule

The SIMD version has one instruction (add_sub_i), and multiple data inputs: a, b, and outputs: y (parameterized by NUM_ALU).

Regards,

Mark

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Visitor
Visitor
197 Views
Registered: ‎02-11-2020

Re: SIMD Architecture

Thanks

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