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Visitor
Visitor
1,600 Views
Registered: ‎10-30-2018

SpyGlass -> added value

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Hi All,

 

What's the added value of the SpyGlass to the Xilinx flow? How could the tool help?

 

What can SpyGlass do over that Vivado cannot?

 

Thank you

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Adventurer
Adventurer
1,570 Views
Registered: ‎01-19-2018

ldm@c,

 

Spyglass is a Linting Tool.

Running a Lint program over your source code, helps to ensure that source code is legible, readable, less polluted and easier to maintain. lint is a tool that is used to mark the source code with some suspicious and non-structural (may cause bug).

 

Yes you can run your RTL through Spyglass after simulation and before synthesis. I don't think it brings any bigger value (given the license costs for the Lint tool) to FPGA design flow.  In FPGA flow Linting tools are very less used.

 

 They are used mostly (almost always I should say) in ASIC design flows.

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Voyager
Voyager
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Registered: ‎08-16-2018

First time I hear of. Apparently a "design and coding guideline checker" - Vivado has the Report Methodology, I wonder how they compare.

 

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Adventurer
Adventurer
1,571 Views
Registered: ‎01-19-2018

ldm@c,

 

Spyglass is a Linting Tool.

Running a Lint program over your source code, helps to ensure that source code is legible, readable, less polluted and easier to maintain. lint is a tool that is used to mark the source code with some suspicious and non-structural (may cause bug).

 

Yes you can run your RTL through Spyglass after simulation and before synthesis. I don't think it brings any bigger value (given the license costs for the Lint tool) to FPGA design flow.  In FPGA flow Linting tools are very less used.

 

 They are used mostly (almost always I should say) in ASIC design flows.

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Contributor
Contributor
1,539 Views
Registered: ‎09-01-2015

Putting aside the cost of the tool ....

 

It's rediculous to say that a tool like spyglass is not important to an FPGA. Lint issues can be design bugs and your simulation environment may not catch these.

 

Linting tools are as important as verification to both FPGAs and ASICs.

 

Mike

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Visitor
Visitor
1,532 Views
Registered: ‎10-30-2018

Could you please provide an example of the RTL bug, which could be catch by SpyGlass, but not by a simulation (besides CDC)?

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Contributor
Contributor
1,513 Views
Registered: ‎09-01-2015

One thing I can think of is if you have a equation where the RHS is bigger than the LHS. The verilog LRM allows this and will truncate the RHS. This may not be what you want and simulation may or may not catch this.

 

Mike

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Visitor
Visitor
1,484 Views
Registered: ‎10-30-2018

What is RHS and what is LHS?

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Contributor
Contributor
1,469 Views
Registered: ‎09-01-2015

RHS - right hand side

LHS - left hand side

This is in reference to the equal sign in an equation.

 

Mike

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