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Registered: ‎03-13-2019

Subtractor question!!!!!!!!!!!!!!!!!!

Hello guys,

I have very weird and silly doubt please help me with it.

What is the best way to use for subtractor

Code snippet #1

module test(
input a,
input b,
output y

assign y = a-b;

Code #2

module test2(
input a,
input b,
output diff,

output borrow

assign diff = a^b;

assign borrow = ~a&b;


Currently I am only considering the diff in the 2 code.

When we consider both example difference output will be same for 1 bit case.
I generated harware for first code and the contents of the schematic is not clear.
Can someone guide me through it?

Thank you

0 Kudos
2 Replies
Registered: ‎07-09-2009

What are you trying to do 

     I 'm guessing your background is software programming,

     In RTL your describing hardware,

e.g. the width of the data is defned by you, its not "just" 8, 16 or 32 bits, it could be say 13 bits,

also, the hardware to a first level, implements the code you describe,

   so you can make code to obfuse that you want a subtractor, and the compiler will implement that code, not realisng that you have made a subtractor,

Dont get me wrong, 

   the compilers are getting better all the time, 

        but are hampered by the fact FPGA's are BIG multi parallel objects, and the main expertise on compiler / optimisers is on single or a few thread CPU, 

     which is Very different to RTL / FPGA's


  think what hardware you want, and code to make that ,


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Registered: ‎01-23-2009

Trying to understand structure of a subtractor using only one bit is more or less meaningless - you need to use wider operations to see the difference. In fact, the tools will generate very different implementations if the width of the arithmetic operation is below a threshold (it used to be 4 bits, but it is probably larger in newer technologies).

However, in general, the answer is to specify what you need at the highest level of abstraction possible and let the tools figure out how to implement it. For addition and subtraction this means using the + and - operator.

The FPGA slice has dedicated cells for implementing addition/subtraction (the carry chain made up of the CARRY4 or CARRY8 cells, depending on the device) - these will be much faster than any other implementation you can come up with (again, assuming the operation is more than a few bits wide). These are inferred whenever a + or - operation is encountered in the code.

If you try and microarchitecture the addition/subtraction you will end up with one of two results:

  • The tools can figure out that this can be implemented in the CARRY4/CARRY8 and you will end up with exactly the same performance
  • The tools will not figure it out and will implement your microarchitected code using LUTs which will be much slower

So just use the + and -.