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Registered: ‎08-07-2018

The best way to perform a frequency divider and obtain a resolution of 1 Hz.

Greetings ... as you can, I am a newbie in VHDL and Vivé and I would like to know the best way to make a frequency divider and obtain a range between 19.5 and 40 MHz selectable with a resolution of 1 Hz. The objective of this divider is the frequency of being able to change the transmission frequency of a HOTLink II transceiver (CYP15G0403DXB).

Any help is welcome. Thanks in advance.

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Registered: ‎01-08-2012

That datasheet says "REFCLKx jitter tolerance / Phase noise limits TBD".  Great.

The jitter requirement will determine which frequency divider architectures can be used.  I guess that the jitter requirement is tight enough to rule out simple FPGA-based divider approaches (such as a phase accumulator).

Do you need rapid frequency agility?  If not, one of the many programmable crystal oscillators would work fine.  These have a fixed frequency crystal or MEMS oscillator and a fractional-N PLL in the one package.  Several Xilinx dev boards use I2C programmable oscillators from Silicon Labs.  They would probably work for you too.

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