11-17-2020 09:11 AM
In the device view after VIVADO has completed FPGA placement and routing, I found that some logic resources are marked in orange (but we haven't marked the relevant colors by ourselves before). The logic in the default state should be blue, so what does the orange logo given by VIVADO mean?
11-17-2020 09:44 AM
The orange color usually means a cell is fixed. As described on page 133 of UG904(v2020.1), fixed cells are those that you have placed yourself, or the location constraints for the cells have been imported from an XDC file.
11-17-2020 09:48 AM
These are fixed cells. You can check the Device view settings to find the various color assigned to objects:
11-17-2020 09:35 PM - edited 11-17-2020 09:36 PM
Thanks for your answers!
In fact, we have not manually set the layout of such logical units, nor have we made relevant physical constraints in any xdc file in the VIVADO project. This is a partially reconfigurable design for testing the MPSoC platform. The only layout constraint is the pblock constraint on the logic of the dynamic area, and it seems that the orange logic is close to the periphery of the dynamic logic area. In addition, we carefully checked the logic modules to which these orange logics belong. They have Interconnect modules and ILA modules, and most of the logic of these modules is still blue. The distribution of orange logic does not seem to have any obvious rules. Why do these orange fixed-layout logic units appear "automatically"?