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Adventurer
Adventurer
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Registered: ‎03-28-2020

The color under the view after FPGA placement and routing

In the device view after VIVADO has completed FPGA placement and routing, I found that some logic resources are marked in orange (but we haven't marked the relevant colors by ourselves before). The logic in the default state should be blue, so what does the orange logo given by VIVADO mean?

mmexport1605632900692.png
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Registered: ‎01-22-2015

@wuyouniyanhu 

The orange color usually means a cell is fixed. As described on page 133 of UG904(v2020.1), fixed cells are those that you have placed yourself, or the location constraints for the cells have been imported from an XDC file.

Cheers, Mark

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Moderator
Moderator
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Registered: ‎01-16-2013

@wuyouniyanhu 

 

These are fixed cells. You can check the Device view settings to find the various color assigned to objects:

syedz_0-1605635306751.png

 

--Syed

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Adventurer
Adventurer
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Registered: ‎03-28-2020

Thanks for your answers!

markg@prosensing.com  @syedz 

In fact, we have not manually set the layout of such logical units, nor have we made relevant physical constraints in any xdc file in the VIVADO project. This is a partially reconfigurable design for testing the MPSoC platform. The only layout constraint is the pblock constraint on the logic of the dynamic area, and it seems that the orange logic is close to the periphery of the dynamic logic area. In addition, we carefully checked the logic modules to which these orange logics belong. They have Interconnect modules and ILA modules, and most of the logic of these modules is still blue. The distribution of orange logic does not seem to have any obvious rules. Why do these orange fixed-layout logic units appear "automatically"?

20201118133234.png
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