Trouble with JK Flip-Flop

[bhoblin2013]

I'm having trouble finishing a JK Flip-Flop and I could really use some help finding what I'm missing. This is my code,

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JKFlipFlop is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
clk : in STD_LOGIC;
Q : out STD_LOGIC);
end JKFlipFlop;
architecture Behavioral of JKFlipFlop is
signal data: std_logic;
begin
process (J, K, clk)
begin
if rising_edge (clk) then
elsif (J='0' and K='0'); then
data<=data;
elsif (J='0' and K='1'); then
data ='0';
elsif (J='1' and K='0'); then
data ='1';
elsif (J='1' and K='1'); then
data <= (not data);
end if;
end process;
end Behavioral;

This gives me the following RTL Schematic

Besides the obvious issue that nothing connects, I know from a classmate that it should look like this,

Could someone please help with this?

[svanapar]

@bhoblin2013

All the assignments in your code are to the signal data. You are not assigning the output Q to any thing. That should be causing the issue.

Regards,

Sravanthi

[bhoblin2013]

I think I made the changes you mentioned but I'm still not getting the correct schematic. This is the code as it is now,

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JKFlipFlop is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
clk : in STD_LOGIC;
Q : out STD_LOGIC);
end JKFlipFlop;
architecture Behavioral of JKFlipFlop is
signal data: std_logic;
begin
process (J, K, clk)
begin
if rising_edge (clk) then
elsif (J='0' and K='0'); then
Q <= data;
elsif (J='0' and K='1'); then
Q ='0';
elsif (J='1' and K='0'); then
Q ='1';
elsif (J='1' and K='1'); then
Q <= (not data);
end if;
end process;
end Behavioral;

And this is the new schematic,

I've been looking around at other codes for JK Flip-Flops but they haven't been of any help because they use additional inputs and outputs and because I'm still trying to figure VHDL out. Any further suggestions?

[tud_hartmann · Accepted solution]

@bhoblin2013

I hope I dont do your homework, but here is the corrected part:

...
signal data : std_logic;
...
process (clk)
begin
  if rising_edge (clk) then
    if (J='0' and K='1') then
      data <='0';
    elsif (J='1' and K='0') then
      data <='1';
    elsif (J='1' and K='1') then 
      data <= (not data);
    end if;
  end if;
end process;

Q <= data;

...

Best Regards,

Stephan

[bhoblin2013]

Thanks for the help. Unfortunately this was the last part of a lab that I couldn't finish during the lab. I did the D-Latch and D-Flip Flop but ran out of time on this on part of the lab. This is really just me trying to figure it out for possible future reference. Thanks again

[jayras]

Thanks @tud_hartmann for the code.

I have been struggling with JK flip flop code and doing the same mistake as @bhoblin2013 did.

I got the concept wrong and for future users here is the picture from where you can get the clear concept of jk flip flop:

source: JK flip flop