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dschussheim
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Explorer
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Registered: ‎06-08-2017

UG946 flow not inferring OOC module as black box

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I am trying to modify the script in UG946 to use HD design flow with my modules. When I open the top synthesized design checkpoint, the OOC module is not a black box. In the tutorial, the OOC modules are all black boxes after the topSynth step. Why doesn't this happen with my OOC module?

Thanks for the help.

Daniel

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dschussheim
Explorer
Explorer
751 Views
Registered: ‎06-08-2017

I figured it out:

In the tutorial there is a top.prj file, and .prj files for each OOC module.

In the top.prj the have lines like:

verilog work "hdl/blackbox/usbf_bb.v"
verilog work "hdl/blackbox/or1200_bb.v"

Where the _bb files are empty. For example.

module usbf(signal names)
<signal declarations>
endmodule

I just did the same thing with the module I wanted to be a black box and it worked.

View solution in original post

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dschussheim
Explorer
Explorer
752 Views
Registered: ‎06-08-2017

I figured it out:

In the tutorial there is a top.prj file, and .prj files for each OOC module.

In the top.prj the have lines like:

verilog work "hdl/blackbox/usbf_bb.v"
verilog work "hdl/blackbox/or1200_bb.v"

Where the _bb files are empty. For example.

module usbf(signal names)
<signal declarations>
endmodule

I just did the same thing with the module I wanted to be a black box and it worked.

View solution in original post

0 Kudos