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Visitor tgillespie
Visitor
635 Views
Registered: ‎05-08-2018

Ultrascale+ SLR hierarchical design

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I'm building a multi-SLR design on the VU13P. I have a submodule that place-and-routes successfully when constrained to the left half of a single SLR, and I want to place 4 copies of this (one in each SLR) in the main design. Is there a way, using the hierarchical design tooling, to place this 4 times without re-placing and re-routing separately for each copy? It seems that, since the SLRs are for my purposes identical, there should be a way of copying the placement and routing configuration from the first copy.

 

The goals here are two-fold:

 

1) Speed up PnR roughly by a factor of 4

2) Give the tooling an easier job during PnR (my design is quite congested, so the router fails when I try to build everything at once).

 

Thanks all!

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Xilinx Employee
Xilinx Employee
575 Views
Registered: ‎11-17-2008

Re: Ultrascale+ SLR hierarchical design

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@tgillespie,

 

Vivado Hierarchical Design does not have a "relocate" feature.  While the silicon layout is identical on each SLR and it may make sense to reuse results from one SLR on each of the others, that capability is simply not part of the toolset.  There is much more to consider, such as how this module connects to the rest of the design, including clocks and IO.  This feature is on our roadmap, but I cannot give you an estimated delivery timeframe.

 

The current HD approach for US+ leverages the Partial Reconfiguration solution, where you break up a design by its hierarchy and implement modules within their own regions.  This allows you to focus on one part of the design at a time, and you can remove completed modules to speed up loading times.  Now, with a heavily congested design, I would recommend using a more traditional approach with pblocks to range modules on the target SLR, coupled with an incremental strategy for subsequent runs.

 

We also support an out-of-context solution where you can implement a submodule of the design on its own, but this approach for UltraScale+ is for analysis only.  Use this OOC solution to tune the RTL and constraints but then merge it back into the full design for full-chip implementation.

 

thanks,

david

1 Reply
Xilinx Employee
Xilinx Employee
576 Views
Registered: ‎11-17-2008

Re: Ultrascale+ SLR hierarchical design

Jump to solution

@tgillespie,

 

Vivado Hierarchical Design does not have a "relocate" feature.  While the silicon layout is identical on each SLR and it may make sense to reuse results from one SLR on each of the others, that capability is simply not part of the toolset.  There is much more to consider, such as how this module connects to the rest of the design, including clocks and IO.  This feature is on our roadmap, but I cannot give you an estimated delivery timeframe.

 

The current HD approach for US+ leverages the Partial Reconfiguration solution, where you break up a design by its hierarchy and implement modules within their own regions.  This allows you to focus on one part of the design at a time, and you can remove completed modules to speed up loading times.  Now, with a heavily congested design, I would recommend using a more traditional approach with pblocks to range modules on the target SLR, coupled with an incremental strategy for subsequent runs.

 

We also support an out-of-context solution where you can implement a submodule of the design on its own, but this approach for UltraScale+ is for analysis only.  Use this OOC solution to tune the RTL and constraints but then merge it back into the full design for full-chip implementation.

 

thanks,

david