cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
1,969 Views
Registered: ‎11-08-2017

[VHDL] Signals Assignment in Package -> how to?

Jump to solution

Hi All,

 

I know it's possible to declare signals in the package. But is it possible to assign the signals inside of the packages?

 

I'd like to write something like following:

package pkg_signals is   
   type plan_t is (A, B);
   signal plan : plan_t;
signal sel : std_logic; end package pkg_signals; package body pkg_signals is plan <= A when sel = '1' else B; end pkg_signals;

Actually the plan_t is enum type... How can I compare enum types?

 

Can I write something like this:

 

signal abc : std_logic;
abc <= '1' when (plan = A) else '0';

 

Thank you!

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Teacher
Teacher
2,732 Views
Registered: ‎07-09-2009

You seem to be doing some logic in the package 

 

that would normaly be in the architecture of the design,

 

If you do need this logic in a package, 

   then you need to write it as a function or procedure in the package. 

      and call that from your architecture.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

0 Kudos
2 Replies
Highlighted
Adventurer
Adventurer
1,917 Views
Registered: ‎11-08-2017

Is it possible to assign signals inside of the packages? How? Please provide some example. Thanks

0 Kudos
Highlighted
Teacher
Teacher
2,733 Views
Registered: ‎07-09-2009

You seem to be doing some logic in the package 

 

that would normaly be in the architecture of the design,

 

If you do need this logic in a package, 

   then you need to write it as a function or procedure in the package. 

      and call that from your architecture.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

0 Kudos