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[VHDL] how to manage lib name depending on the design entry?

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Observer
Posts: 37
Registered: ‎11-08-2017

[VHDL] how to manage lib name depending on the design entry?

Hi All,

 

I want to use the different library names for the same 

 

Le's say I have a VHDL file with the following lines:

 

library mylib_1;
use     mylib_1.abc.all;

 

But, when I'm going to use the same file for another design, I want this library will be named differently:

library mylib_2;
use     mylib_2.abc.all;

I don't want to edit this file depending on what design this file is going to be used. 

 

So, how should I manage this issue? Is it possible to do this using configurations? How?

 

Thank you!

 

Moderator
Posts: 2,336
Registered: ‎11-09-2015

Re: [VHDL] how to manage lib name depending on the design entry?

Hi @dmitryl_home,

 

I don't really understand what is your goal for using the same library/package with a different name...

 

Could you give more detail why it wouldn't work with the same names? Why not keeping the names of the libraries between project? 

 

Regards,

Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Posts: 37
Registered: ‎11-08-2017

Re: [VHDL] how to manage lib name depending on the design entry?

The unit includes packages of functions and procedures, which should be referenced inside of the files.

 

For example:

 

 

library pkgs;
use     pkgs.all;

 

 

But, then I integrate the unit into the higher hierarchy, this hierarchy also has a reference to the 'pkgs' library...

 

So how to solve this situation (same library names in different hierarchies/files, which should actually point to the different libraries)?

 

Probably is it possible to manage this situation in the following manner:

 

library unit1_lib;
use     unit1_lib.pkgs.all; 

library unit2_lib;
use     unit2_lib.pkgs.all; 

 

 

But, how can I create a library inside of another library (e.g. library 'pkgs' inside of library 'unit1' and then a library 'pkgs' inside of library 'unit2')?

 

Thank you!

Explorer
Posts: 210
Registered: ‎09-07-2011

Re: [VHDL] how to manage lib name depending on the design entry?

Library names are global and flat at the top-level of the environment... so can't be nested.

 

You could compile the utility packages for a unit in the same library as the unit.   The unit just has to say "use work.all" to see all the packages.  This way, the unit doesn't care/know about it's actual library name.

 

So, unit1 and all its packages can be compiled into library unit1_lib.  Internally though, the unit1 code just uses "use work.all".

 

Other units, like unit2 can be arranged the same way.  It's own packages are in "work" .  To use unit1, it just needs to reference library unit1_lib.