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Observer tip.can19
Observer
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Registered: ‎10-23-2018

Verilog - 2005: Why output port cannot be connected to reg data type?

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I might understand that as per Verilog standards output ports cannot be instantiated to a reg data type output port. Just wanted to know why and if there is any reason for this?

An example is below which when run in Vivado 2019.1 gives error:

module test_op (a);
output reg a;
t_ff(.b(a));
endmodule
..
..
module t_ff (b);
output b;
endmodule

[Synth 8-685] variable 'a' should not be used in output port connection.

Any idea why this is followed?

Thank you.

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1 Solution

Accepted Solutions
162 Views
Registered: ‎01-08-2012

Re: Verilog - 2005: Why output port cannot be connected to reg data type?

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It's just one of those things in the language defintion.

(System)Verilog created the logic type to overcome this limitation.   It's like a VHDL signal in that regard.

Perhaps you should be using logic instead.

View solution in original post

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1 Reply
163 Views
Registered: ‎01-08-2012

Re: Verilog - 2005: Why output port cannot be connected to reg data type?

Jump to solution

It's just one of those things in the language defintion.

(System)Verilog created the logic type to overcome this limitation.   It's like a VHDL signal in that regard.

Perhaps you should be using logic instead.

View solution in original post

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