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Visitor
Visitor
407 Views
Registered: ‎09-23-2019

Vivado 2020.1 synthesized away signals with KEEP attribute and strange FOR GENERATE behavior

 

Hi,

I'm working on the register delay chains, but I'm running into some issues with FOR GENERATE.

 

This is what I want to do. But vidado completely synthesized away my BUF(...) and also FOR GENERATE blocks. How can I prevent vidado from removing my BUF?

myfingerhurt_0-1602230932863.png

 

This is how my code looks like. 

 

    ----------------------------------------------------------------------------
    -- CONSTANT
    ----------------------------------------------------------------------------
    constant T0 : integer := 0; -- Delay
    constant T1 : integer := 1; -- Delay
    constant T2 : integer := 2; -- Delay
    constant T3 : integer := 3; -- Delay

    ----------------------------------------------------------------------------
    -- COMPONENT
    ----------------------------------------------------------------------------
    dn : chain_regs
        GENERIC MAP(
            n          => n, 
            t          => 3,
            simulation => simulation
            )
        PORT MAP(
            MRST_N   => MRST_N       ,
            CLK_T(0) => '0'          ,
            CLK_T(1) => CLK_T(T2)  ,
            CLK_T(2) => CLK_T(T3)  ,
            CIN      => std_logic_vector(to_unsigned(0 , n)),
            DIN      => U_DQ_IN      ,
            DOUT(0)  => open         ,
            DOUT(1)  => open         ,
            DOUT(2)  => FIN_DAT      
        );
        

 

 

I have KEEP attribute assigned to BUF and DOUT

-----------------------------------------------------------------------
-- LIBRARY
-----------------------------------------------------------------------
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package typdef_pkg is
        type bus_array is array(natural range <>) of std_logic_vector;
end package;

-----------------------------------------------------------------------
-- LIBRARY
-----------------------------------------------------------------------
LIBRARY IEEE;
use ieee.std_logic_1164.all;
USE IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- use ieee.std_logic_arith.all;
use work.typdef_pkg.all;

-----------------------------------------------------------------------
-- ENTITY
-----------------------------------------------------------------------

ENTITY chain_regs IS --
    GENERIC(
        CONSTANT n    : positive := 18;  -- How many bits available in this DPRAM.
        CONSTANT t    : positive := 2;  -- Stages of this register chain.
        CONSTANT simulation : boolean := FALSE 
        );
    PORT(
        SIGNAL MRST_N     : IN    std_logic;
        SIGNAL CLK_T      : IN    std_logic_vector;
        SIGNAL CIN        : IN    std_logic_vector;
        SIGNAL DIN        : IN    std_logic_vector;
        SIGNAL DOUT       : OUT   bus_array(t-1 downto 0)(n-1 downto 0)
        );
end chain_regs;
-----------------------------------------------------------------------
-- ARCHITECTURE
-----------------------------------------------------------------------
architecture rtl of chain_regs is
    ----------------------------------------------------------------------------
    -- CONSTANT
    ----------------------------------------------------------------------------
    
    
    ----------------------------------------------------------------------------
    -- SIGNAL
    ----------------------------------------------------------------------------
    SIGNAL buf : bus_array(t-1 downto 0)(n-1 downto 0);
    SIGNAL CLK : std_logic_vector(t-1 downto 0);
    
    ----------------------------------------------------------------------------
    -- DEBUG
    ----------------------------------------------------------------------------
    attribute mark_debug : string;
    attribute keep : string;
    attribute keep of buf     : signal is "true";
    attribute keep of DOUT    : signal is "true";

begin
    ----------------------------------------------------------------------------
    -- ASSIGN
    ----------------------------------------------------------------------------
    CLK  <= CLK_T;
    dout <= buf ;
    
    ----------------------------------------------------------------------------
    -- Bus DATA Sync
    ----------------------------------------------------------------------------
    PROCESS (DIN)
    BEGIN
          
        buf(0)   <= DIN  ; 
            
    END PROCESS;

    ----------------------------------------------------------------------------
    -- Bus DATA Sync
    ----------------------------------------------------------------------------
    cas : FOR I IN 1 TO t-1 GENERATE
        PROCESS (MRST_N, CLK(I))
        BEGIN
        
            IF(MRST_N ='0')THEN -- Master Reset
                buf(I)  <= CIN;
                    
            ELSIF(CLK(I)'EVENT AND CLK(I)='1')THEN
                buf(I)   <= buf(I-1)  ; 
                
            END IF;
        END PROCESS;
    END GENERATE;

end rtl;

 

 

 

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4 Replies
Highlighted
Scholar
Scholar
398 Views
Registered: ‎08-07-2014

@myfingerhurt ,

Maybe this will help - https://www.xilinx.com/support/answers/54778.html

 

------------FPGA enthusiast------------
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Highlighted
Visitor
Visitor
384 Views
Registered: ‎09-23-2019

Thank you for your reply, but I have already tried that.

 

KEEP, DONT_TOUCH none of these worked.

attribute mark_debug : string;
attribute dont_touch : string;
attribute keep : string;
attribute keep of buf : signal is "true";
attribute keep of DOUT : signal is "true";
attribute keep of DIN : signal is "true";
attribute dont_touch of buf : signal is "{true|false}";

 

I also have tried this, failed on the compilation.

library synplify;
use synplify.attributes.all;

attribute syn_keep of buf : signal is true;

 

 

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Highlighted
Visitor
Visitor
259 Views
Registered: ‎09-23-2019

I have no idea, why my last post disappeared?

 

I have changed my latest code and skipping the synthesized away issue for now.

But I have another problem. Here you can see. My original VHDL was trying to do this. 

buf_reg[0] to CLK[0], 

buf_reg[1] to CLK[1], 

buf_reg[2] to CLK[2].

Since the CLK[1] & CLK[2] were from the same source, so the vivado merged them into CLK[1], and connected CLK[1] to buf_reg[0] & buf_reg[1], left the buf_reg[2] connect with CLK[0].

So the synthesized result completely violates my original design.

Question: How can I keep vivado from swapping my CLK[]?

2020-10-12 16_12_22-X_CY7C0852- Vivado 2020.1.png

    dn : chain_regs
        GENERIC MAP(
            n          => n, 
            t          => DAT_STAGES,
            inital     => std_logic_vector(to_unsigned(0 , n)),
            simulation => simulation
            )
        PORT MAP(
            MRST_N   => MRST_N       ,
            CLK_T(0) => CLK_T(T2)  ,
            CLK_T(1) => CLK_T(T1)  ,
            CLK_T(2) => CLK_T(T1)  ,
            DIN      => U_DQ_IN      ,
            DOUT(0)  => wDFF_DOUT(0) ,
            DOUT(1)  => wDFF_DOUT(1) ,
            DOUT(2)  => wDFF_DOUT(2)      
        );
        
        FIN_DAT <= wDFF_DOUT(2);

 

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Highlighted
Visitor
Visitor
213 Views
Registered: ‎09-23-2019

Thanks to my local technical support, I finally get it working. 

 

They said that the std_logic_vector in my definition was in default (0 to 2)  order.

So the CLK was assigned in backward, and that was the problem.

 

And I solved my problem by changing my port definition explicit into this st_logic_vector(t-1 downto 0).

ENTITY chain_regs IS --
    GENERIC(
        CONSTANT n    : positive := 18;  -- How many bits available in this DPRAM.
        CONSTANT t    : positive := 2;  -- Stages of this register chain.
        CONSTANT inital : std_logic_vector ;  -- Default initial.
        CONSTANT simulation : boolean := FALSE 
        );
    PORT(
        SIGNAL MRST_N     : IN    std_logic;
        SIGNAL CLK_T      : IN    std_logic_vector(t-1 downto 0);
        SIGNAL DIN        : IN    std_logic_vector(n-1 downto 0);
        SIGNAL DOUT       : OUT   bus_array(t-1 downto 0)(n-1 downto 0)
        );
end chain_regs;
-------------------

 

 

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