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Adventurer
Adventurer
752 Views
Registered: ‎09-14-2018

Vivado Block Diagram re-use process

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I need to reuse a block design in a new Vivado project. I want to replace all IPs in block diagram with new ones (first, keeping all connections the same). What is the process? Actually, this is more global question how to easily reuse BDs.

I tried manually to update .bd file in text editor (changing IP properties like vlnv, paths, names and etc.) but failed.

The design has a single BD with multiple custom and Xilinx IPs hooked up via AXIs or directly. Not sure if such details matter.

Thank you. 

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Xilinx Employee
Xilinx Employee
508 Views
Registered: ‎06-13-2018

Re: Vivado Block Diagram re-use process

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Hello Alex,

1. In case of the same Kintex 7 family (from xc7k325 to xc7k160). I assume the following steps: Create a new design. Copy all sources (custom and Xilinx IPs) and BD keeping the same file structure. Replace .xdc file and manually modify .bd (replace the target device info). Is it correct?

Yes, your understanding is correct. Please check the attached image.

2. From Kintex 7 to Spartan 7. Any differences in a process? Any requirement of replacing IPs (I intend to use resources, supported by both families)?

I would like to suggest just go for the new design because the architecture of both the device is different.

3. What is the process of replacement of AXI based Xilinx IP like MIG_7?

I would like to request that please post this question in AXI Infrastructure. If your issue is resolved, please close this thread by Accepting it as a Solution.

Regards,

Naveen

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11 Replies
Moderator
Moderator
732 Views
Registered: ‎03-16-2017

Re: Vivado Block Diagram re-use process

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Hi @arotenst ,

1. First archive (from Vivado itself) the old BD project (up to date) as a backup. 

2. Remove/delete the IPs and its repositories which you do not want to use from the BD. 

3. Add new custom/Xilinx IPs in your BD. Generate its output prodcuts and create HDL wrapper for your BD manually or automatically. Also Make sure you have validated the BD before doing synthesis. 

 

 

Regards,
hemangd

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Adventurer
Adventurer
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Registered: ‎09-14-2018

Re: Vivado Block Diagram re-use process

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Hi Hemang,

I need to clarify my question. I have a project, which is highly "contaminated" (content a lot of garbage during multi-year development). I need first to create a brand-new project with intent of utilizing the original BD as much as possible (considering minor .bd modification in text editor). All IPs referring to this BD are to be regenerated. What is the process of doing it having in mind I have 0 experience in BD design flow? Xilinx doc says that BD may be re-usable only if keep exactly the same file structure. What does it mean? At what extent?

Not clear why Vivado generates IP folders ending with …0_0,  …_1_0, …_0_1 end etc. Why? Should I copy this? If I should, any explanations why? I prefer to have _0 or _1 at max.

Eventually, I need to create a similar project but for another FPGA target device (same Kintex 7 family). Xilinx says in such case the BD reuse is not possible. Why? How to work around?

I believe Xilinx must have a smart solution to this. Please help with the detailed instructions.

Thank you,

Alex    

 

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Moderator
Moderator
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Registered: ‎03-16-2017

Re: Vivado Block Diagram re-use process

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Hi @arotenst , 

There are two points i would like to mention. For version control please check UG 892 , topic - Recommended Source files to manage. Page. 85 onwards. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug892-vivado-design-flows-overview.pdf#nameddest=xUsingSourceControlSystemsWithTheVivadoTool

This doc will help to manage proper source files for your IPI design. This will also answer about your question on BD reusability upto what extent. 

 

Another point is , if you want to change IPs in your IPI design follow points which i mentioned in my last thread. 

 

For more info. please refer UG 1118. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug1118-vivado-creating-packaging-custom-ip.pdf

 

 

 

Regards,
hemangd

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Adventurer
Adventurer
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Registered: ‎09-14-2018

Re: Vivado Block Diagram re-use process

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Hi Hemang,

Thank you for your input but you did not answer my questions.

I want to create a NEW design and try to re-use a block diagram. Vivado does not allow user even to open BD if something does not match with the used IPs. In my opinion this is not right. As I understand I must copy all old IPs to a new design (before opening BD for the first time) and then replace them with new ones. By the way, before creating new user IPs I have to “clean” the project file structure otherwise I will see multiple .._0_0,  …_1_0, …_0_1 and etc. folders.

Is it way to open BD if IPs do not exist or something is wrong? I do not mean manually modify .bd file as this may be risky.

Another my question was why the same BD cannot be reused for the different target device? My BD is not on the TOP. Here is an example of the empty .bd file (without graphic):  
{

  "design": {

    "design_info": {

      "boundary_crc": "0x0",

      "device": "xc7k325tffg900-2",

      "name": "COSMO_FPGA",

      "synth_flow_mode": "Hierarchical",

      "tool_version": "2018.3"

    },

    "design_tree": {}

  }

}

Is it enough to just replace the device info in the complete .bd file to make it work with different Xilinx parts at least from the same family?

Thank you.

 

   

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Xilinx Employee
Xilinx Employee
627 Views
Registered: ‎06-13-2018

Re: Vivado Block Diagram re-use process

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Hello @arotenst,

From your issue description, I assume and believe that you want to reuse your BD in another design.

Can you please confirm, Are you using the same version of tools to create a new design? If yes, then you need to run the TCL command create_bd_tcl in the old project whose BD you want to use in the new project.

After running this command a TCL file will be generated. You need to source the same TCL file in the new project by source <path_of_the_file>.tcl. After this, you can add/remove the IPs from your BD.

If you are migrating from older Vivado version to Newer, for example, let suppose Vivado 2018.1 to Vivado 2018.3. In this case, you need to add the .bd file of your old project into the new project and then you need to upgrade the IPs. After this, you can add/remove IPs from your BD.

Today at my end I have tested these two solutions and it is working for me.

Can you please let me know what you are doing and what error message you are getting?

Another my question was why the same BD cannot be reused for the different target device?

Different FPGA has different architecture and resources hence we do not suggest customer to use the same BD for the different target device.

Hope this information will help you. Looking forward to hearing from you.

Regards,

Naveen 

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Adventurer
Adventurer
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Registered: ‎09-14-2018

Re: Vivado Block Diagram re-use process

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Hi Naveen,

It looks like create_bd_tcl is an invalid command. I also have not found it or close command in the Xilinx UG835 document.

Here is my case:

I have got a design created in Vivado 2017.2. Later it was upgraded to 2018.3, but the design did not look stable, even I was able to generate the FPGA image. It looked like custom IPs were not completely up to date even Vivado said that. Some issues I saw after innocent tweaking like attempt to update them.

Anyway, I decided to create a new clean project with utilization of the existing BD. I tried to regenerate all custom IPs. Unfortunately, I could not find a way how to open BD if Vivado seeing discrepancies with the cores. So, I started re-drawing the BD, as I also would also need such experience.

I have two relative questions on this:

  1. I need to define new interfaces for example (ARM_BUS and EXP_BUS) (I have attached a snapshot, showing a list of ports in IP). I did not understand all steps to do (I have UG1118). I would expect from Vivado something simple: create a new interface and just move the ports associated to this bus from one window to another. But the tool does not do this.
  2. After making all connections between IPs on BD I need to add IPs for AXI Interconnects (I have two). I was told that this should be done automatically. How to do it?     

 

Regarding the BD adapting for a different target device.

I have Kintex xc7k325 part only because the package size. The device is ~20% full. I plan to reduce a number of signals to fit xc7k160. What is the process of conversion?  BD is not on the top level. Except the RTL files I need to replace .xdc. In BD file there is only line which defines the target device. I just need to replace it, correct? Anything else?

Another goal is to fit into Spartan 7 (no SERDESes). I guess I need just to regenerate all IPs for Spartan with the same parameters (vlnv, rev. and etc..) but with relaxing timing, correct. Anything else?   

P.S. Could you keep this case open as I still want to try BD reuse later.

Thank you,

Alex   

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Adventurer
Adventurer
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Registered: ‎09-14-2018

Re: Vivado Block Diagram re-use process

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Forgot to attach the file.

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Adventurer
Adventurer
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Registered: ‎09-14-2018

Re: Vivado Block Diagram re-use process

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I figured out about a new interface definition. For some reason I had to select all ports to be part of the interface. It looks like Vivado does not allow to add the ports later even the Xilinx doc says opposite, which is totally weird. I am OK with it.

I also figured out about AXI. No concern.

So, main issue is still BD reuse.

 

Thank you,

Alex

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-13-2018

Re: Vivado Block Diagram re-use process

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Hello @arotenst,

Please find the Step by step procedure on how to reuse the Block Diagram.

1. Please create your project and validate it. In my case, I used Vivado 2017.2 and create a small BD example design and validate it.

f_1.PNG

2. Then I created the Wrapper file.

3. I ran the TCL command create_bd_tcl <path>file_name.tcl and successfully generate the tcl file.(In your case it is optional)

4. I open the Vivado 2018.3 and create the project and source the path(old project created with Vivado 2017.2 .srcs folder) for the .bd file and add in the project.

f_2.PNG

5. Then I check the IPs status. It is showing IP is locked. I goto the Report => Report IP status =>  Upgrade selected.

f_3.PNG

6. After selecting on Upgrade Selected IPs, a pop-up window will come with IP Upgrade Completed.

f_4.PNG

This is the procedure to reuse the BD. I personally verified this and it is working for me.

Can you please confirm, are you following the same steps? If yes, Please share the error message which you are getting.

Looking forward to hearing from you.

Regards,

Naveen 

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Adventurer
Adventurer
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Registered: ‎09-14-2018

Re: Vivado Block Diagram re-use process

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Hi Naveen,

Did you mean write_bd_tcl instead of create_bd_tcl? As I wrote earlier create_bd_tcl is not a legal command.
Regarding BD reuse process. I understood the process if I need to make a design in a newer Vivado environment. I do not need to do it now as I already have something running on 2018.3. I am creating a new project from the sources and redo Bock Diagram from scratch, consider it as an exercise.


As I asked I need steps to reuse design for the different target device.
1. In case of the same Kintex 7 family (from xc7k325 to xc7k160). I assume the following steps: Create a new design. Copy all sources (custom and Xilinx IPs) and BD keeping the same file structure. Replace .xdc file and manually modify .bd (replace the target device info). Is it correct?
2. From Kintex 7 to Spartan 7. Any differences in a process? Any requirement of replacing IPs (I intend to use resources, supported by both families)?
3. What is the process of replacement of AXI based Xilinx IP like MIG_7?

Thank you,
Alex

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Xilinx Employee
Xilinx Employee
509 Views
Registered: ‎06-13-2018

Re: Vivado Block Diagram re-use process

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Hello Alex,

1. In case of the same Kintex 7 family (from xc7k325 to xc7k160). I assume the following steps: Create a new design. Copy all sources (custom and Xilinx IPs) and BD keeping the same file structure. Replace .xdc file and manually modify .bd (replace the target device info). Is it correct?

Yes, your understanding is correct. Please check the attached image.

2. From Kintex 7 to Spartan 7. Any differences in a process? Any requirement of replacing IPs (I intend to use resources, supported by both families)?

I would like to suggest just go for the new design because the architecture of both the device is different.

3. What is the process of replacement of AXI based Xilinx IP like MIG_7?

I would like to request that please post this question in AXI Infrastructure. If your issue is resolved, please close this thread by Accepting it as a Solution.

Regards,

Naveen

-------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as a solution.

-------------------------------------------------------------------------------------------------

TEST_F.PNG