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Adventurer
Adventurer
311 Views
Registered: ‎09-14-2018

Vivado External Ports names change

Hello,

In Block Diagram I want to change the external port name (the port is a part of the custom interface). For some reason Vivado (2018.3) does not allow to do this. At least under External Port Properties window. Could you please let me know how to change the names. I hope this is possible.

I have another design (older one) and the names were adjusted. I have attached a file showing a block with the interface and used internal names, the external port in my design and the port with the modified names (another project).   

Thank you.

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2 Replies
Xilinx Employee
Xilinx Employee
295 Views
Registered: ‎01-30-2019

Re: Vivado External Ports names change

@arotenst 

Please read make_wrapper command from UG835, this command makes a top-level wrapper for your Block Designs

using this command make a wrapper(wrapper_1) which will instantiate your block design and then make another wrapper (wrapper_2). 

Now use these wrapper such that wrapper_1 is instantiated in wrapper_2. and now using port mapping in instantiations you can rename the top level ports in wrapper_2 as per your convinence.

--Suraj

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Adventurer
Adventurer
243 Views
Registered: ‎09-14-2018

Re: Vivado External Ports names change

I already have the Top Level FPGA file. I had to change the name in that file to generate the image. My intention was to change the names on the wrapper 1 level. I know that this somehow was done by the person who originally did a design. Also, I almost positive that this was done in GUI. Any suggestions?

Thank you.

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