12-06-2017 12:54 PM
I'm wondering if the Vivado block design methodology is compliant or not with the DO-254 standards, specifically for top level generation, and pre-compiled IP Blocks like AXI and Xilinx's primitives.
12-06-2017 07:07 PM
The tool is DO-254 compliant. Please take a look at the attached snapshot from https://www.xilinx.com/support/documentation/white_papers/wp401_DO254_FPGA_Designer.pdf
Coming to IPs, we have IPs that are specially certified for DO-254. I would recommend you to go to https://www.xilinx.com/member/avionics/index.htm for more detailed information.
12-07-2017 06:55 AM
Thank you for the quick response, I agree with your answer about Xilinx's tools DO-254 compliance, but what about the IPs in the "IP Catalog" feature whether the IPs are Xilinx's (especially for the AXI IP) or third party one, are they certified under the DO-254?
12-11-2017 05:34 AM