08-19-2018 05:09 PM
Why is the LEC (Logic Equivalent Check) needed in the FPGA Flow? There is no a P&R stage (as in ASIC flow)...
Is it not enough just to check the logs and reports of the synthesis tools in order to see the RTL was synthesized without problems?
Why is the LEC stage involved in the FPGA flow? When is it required?
08-20-2018 12:59 AM
Why not? In FPGA flow, you have synthesis, placement, logic optimization, etc...
I find it totally justified... (regarding the rising complexity of the designs nowadays.)
08-20-2018 02:37 AM
OK, so why LEC is needed at all? Each tool checks itself (synthesis tool, placement tool, etc). Are they not realable?
Could you probably provide an example when LEC can help, but other tools cannot?
08-20-2018 08:39 AM
For instance, how can you be sure the synthesis checks his job correctly? Can you certify vivado is bug free?
I've seen, in the past, tools iserting functional bugs in RTL code during synthesis (inverting logic on a output pad). The synthesis tool was not complaining at all.
Of course the tool will perform *some* checks but it won't be fully reliable.
At least a LEC tool is not using the same algorithm. It's an independent check.
08-27-2018 01:40 AM
How the FPGA flow different from the ASIC flow from LEC point of view.
In ASIC flow, the LEC is involved in the post P&R stage while in FPGA is rarely used. The only difference is so that in FPGA all the cells are already placed, but in both flows there is a chance that routing will be wrong and not equivalent to RTL.
So, I still look for a realable answer with a good explanation why in FPGA flow the LEC is not involved while in ASIC it does...
Can anyone response?
08-31-2018 03:37 PM
Here's my two cents. In ASIC flows, there's a lot more 'things' that touch the netlist post synthesis. Things for DFT, scan insertion, BIST, various and sundry physical optimizations, etc, etc. Even manual tweaks.
LEC is a powerful tool during during all these post-synthesis touches, to make sure nothing went wrong. The first stage RTL->gate LEC check is a prerequisite for all of this - and this LEC check is usually the HARDEST one to setup and verify.
None of the post-synthesis optimization steps are done (or least none done in a netlist-visible form) in FPGA design. So there's not much to compare in an LEC flow for FPGAs - other than the first (very difficult) step of an RTL->gates comparison.
And if that's the only step you're going to do, then all you're doing is a QC check on the vendors (Xilinx Vivado) synthesis tool.
Now I used to argue that QC check is quite pointless - or at least mostly busy work. You have to trust your vendor at some point. And RTL->gate mismatches used to be an extremely rare event - in my experiences Now with Vivado being still being a quite new codebase, and its continuing to expand in it's language feature support - I've submitted a few Vivado synthesis RTL/gate mismatches SRs in the past 4-5 years. LEC would have caught those, had we run it.
I'm still on the fence with Vivado and the requirement of LEC. It's a nice to have - but NOT easy to setup.We don't do it, but I often wonder if it'd be worth the pain.