05-06-2019 01:53 PM
I had to re-generate the old Xilinx IPs for various clocks, BRAMs, FIFOs. I noticed that the .xci files look very much different. The new generated files are full of AXI related information. What is the reason of it? I do not see any AXI options while doing customization.
I wanted attached the .xci files as examples but Xilinx tool does not allow it (even renamed as .txt) .
05-07-2019 01:58 PM
I'm not sure I understand. Are you asking for basic IP without AXI support, or with? If you don't want the AXI support, feel free to look through the libraries guide and instantiate those components however you want them from RTL.
05-07-2019 02:08 PM
I do not want AXI support for the basic memory/FIFO. For some reason a new generated .XCI files have a big portion of with AXI LITE information. I do not understand why. I do not see any AXI option when I generated a product (and should not expected it). .veo files (instantiations) look similar to the old ones. The huge difference between the old and new .xci files makes me think that just a simple IP upgrade (in general) may not be safe enough.
PS I do not understand why Xilinx does not allow me to attach a sample of .xci even after changing the file extension to .txt.
05-07-2019 03:39 PM
I don't use AXI myself, and I enjoy building components that don't have it within them.
You can find a discussion regarding how to build block RAM or FIFO components, including code, at ZipCPU.com. If you don't want an AXI interface to them, place whatever interface you'd rather have on them.
To be honest, I don't even know what a .xci file is--I don't use them, or at least I don't use them knowingly. All of my work is done at the RTL level.
05-07-2019 03:53 PM
Thank you, Dan. Honestly, I expected Xilinx support guys to respond.
I also used to do almost everything at RTL level. Now I have to re-use a heavily IP based block design project. My question was just for my information. How come a new generated Xilinx IP (.xci) has a lot not related to this IP information. May be Xilinx just tried to combine AXI based BRAM with a general BRAM.