I am coming from the Altera/Intel flow and therefore getting familiar now with Xilinx flows. One thing i was wondering is how to prevent polution of my timing constraint file when I add debug cores.
I use a separate xdc for pinning and one separate for timing constraints. However, when I add debug cores to my design then the timing constraints file (which is set as target) becomes highly poluted with all stuff related to these cores.
How can I prevent that? What is the normal approach there?