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Observer
Observer
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Registered: ‎02-01-2019

debugging and xdc file polution

Hi Guys,

I am coming from the Altera/Intel flow and therefore getting familiar now with Xilinx flows. One thing i was wondering is how to prevent polution of my timing constraint file when I add debug cores.

I use a separate xdc for pinning and one separate for timing constraints. However, when I add debug cores to my design then the timing constraints file (which is set as target) becomes highly poluted with all stuff related to these cores.

How can I prevent that? What is the normal approach there?

Regards

Henk

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Moderator
Moderator
229 Views
Registered: ‎11-04-2010

You can try to create a new empty XDC and set it as target XDC.

Then all the new generated debug related constraints will be saved to this new XDC.

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