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Visitor
Visitor
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Registered: ‎11-19-2019

partial reconfiguration to reuse the partition

I'm using the pr process mainly to get the benefit of partition, we don't really need to reconfigure the part in the work place.

 

Instead of locking the static design part, what I really want is to lock the placement and route of the reconfigure module , and save a checkpoint for future reuse.

 

In this case, is it possible if I do not use the partial reconfiguration procedure? Is there any other way to achieve this goal?

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Moderator
Moderator
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Registered: ‎05-08-2012

Hi @zhihuacai 

There is a module reuse flow available for 7-Series architectures as described in UG905 which uses a locked placed and routed module for use with a top-level design. This is not supported for the UltraScale UltraScale Plus architectures at this point though. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug905-vivado-hierarchical-design.pdf

 

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Visitor
Visitor
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Registered: ‎05-11-2017

Hi @marcb ,

I am using Ultrascale+ device and I am trying to achieve something similar. I want to preserve the routing and placement in the reconfigurable area and save it as a DCP. I want to re-use this DCP in my later builds. I am just trying to achieve the "hierarchical design flow" using PR and I do not want to use the dynamic exchange functionality.

I tried combining the incremental design methodology along with the partial-config flow and it does not work. I get errors in the implementation of some of the boundary pins.

My current problem is, I build my designs on the build-server and it takes a lot more time than the builds without PR. So my idea is, If I can re-use some part of the design then the build time would improve.

So my question is:

If I want to re-use the part of the design to improve my build time, Is there a workaround, or what does Xilinx recommend in such scenarios? 

Thank you!

Regards,
Narahari

PS: @zhihuacai please mark it as solved so that this answer appears on the top in the forums, it took me 2 days of browsing through all the answers to get here. I am sure there are many clueless engineers still out there who can benefit from your post