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Registered: ‎12-05-2019

report_design_analysis -congestion

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Dear all,

I have congestion problems in my design. I already saw several posts on that and several guides. I used them to modify part of my design and it works. I mean, it looks like I am on the right path event if there is still congestion. However, it is not fully clear the results of the

report_design_analysis -congestion

command. I already saw the link

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug906-vivado-design-analysis.pdf#page=120 

posted in another post, but it looks like there is not an answer for me.

I would like to know:
1) Placed Maximum Level Congestion Reporting: does it represent the congestion due to physical block placed (such as LUT, MUX, RAM, DSP)? I guess it does not take into account the routing right? It shows the congestion in terms of "blocks", correct?  The percent of LUT, DSP, MUX etc.. is the percent of block used in that direction?

2) Initial Estimated Router Congestion Reporting: it is "real" or only "Estimated"? can I neglect it?

3) Routed Maximum Level Congestion Reporting: it shows different results from "Initial Estimated..": in my case I have in the "Estimated" part a level 6 congestion on North Global and North Long, but in the "Routed Maximum...Report" the congestion Level In North direction is 2...which is right? both? Also the Congestion Windows are different...

4) Placed Tile Based Congestion Metric (Vertical/Horizontal): this is (maybe) the clearest..it shows the Tile congestion and it can be also seen by the GUI...it is not clear the Placer Max overlap? what it refers to?

Is there a guide, a post or a Xilinx Answer explaining point per point the result of the congestion report analysis?

Thanks for your help.

A.

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Highlighted
Visitor
Visitor
53 Views
Registered: ‎12-05-2019

As usual...

a few pages below in UG906 vivado design analysis all points are explained...

View solution in original post

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Highlighted
Visitor
Visitor
54 Views
Registered: ‎12-05-2019

As usual...

a few pages below in UG906 vivado design analysis all points are explained...

View solution in original post

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