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Observer kuki
Observer
601 Views
Registered: ‎05-24-2018

set_max_delay for neighborhood Partial Reconfiguration Partitions

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Hi,

 

The setup is the following:

Architecture UltraScale+

Vivado 2017.4

Project (GUI) mode, though eventually will shift to Batch mode.

 

I have a design pretty congested / packed with multiple Reconfiguration Partitions (RPs)

To utilize the area as much as possible there are direct connections between RPs.

One of the warnings highlighted by the tool:

Direct paths between two RPs  
Signal 'data[0][110]' is a direct path that connects Reconfigurable Partition 'u_dummy_box_0' and 'u_dummy_box_1' without a synchronous timing point in the static design. This omission may lead to timing failures in hardware depending on the Reconfigurable Modules that are currently loaded. To close timing on all possible synchronous paths, ensure that any possible path contains at most a segment in only a single Reconfigurable Partition.
Related violations: <none>

This is pretty obvious that depending on the combination of neighborhood Reconfigurable Modules the timing path on those connection points may fail, so to make sure that does not happen I would like to apply extra constraints through "set_max_delay" command.

I have got FFs on both sides of neighborhood RPs. Unfortunately it is not possible to use "set_max_delay" to constraint paths between FF and input / output pins of RPs.

 

Can the experts please help me to find a solution for this issue?

I really don't want to add FF stage in static region between RPs, as that will affect already congested resources.

 

Thanks.

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1 Solution

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Moderator
Moderator
577 Views
Registered: ‎11-04-2010

Re: set_max_delay for neighborhood Partial Reconfiguration Partitions

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Hi, @kuki ,

In UG909, you can see such behavior is not recommended.

For design with multiple RPs, Xilinx recommends not having direct connections between two RPs.

The dillema you met is one of the reason for not recommending.

 

The input/output of RP is interconnection, which cannot be used as reasonable endpoint for set_max_delay, as you mentioned.

You can try to add set_max_delay from FF to FF constraint in the initial configuration, and consider to lock the 2 FFs in 2 RPs in the later configuration if there is no timing violation in the intial configuration. 

You should confirm that in the all RMs of RPs, the FFs in the boundary should always be used.

 

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2 Replies
Moderator
Moderator
578 Views
Registered: ‎11-04-2010

Re: set_max_delay for neighborhood Partial Reconfiguration Partitions

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Hi, @kuki ,

In UG909, you can see such behavior is not recommended.

For design with multiple RPs, Xilinx recommends not having direct connections between two RPs.

The dillema you met is one of the reason for not recommending.

 

The input/output of RP is interconnection, which cannot be used as reasonable endpoint for set_max_delay, as you mentioned.

You can try to add set_max_delay from FF to FF constraint in the initial configuration, and consider to lock the 2 FFs in 2 RPs in the later configuration if there is no timing violation in the intial configuration. 

You should confirm that in the all RMs of RPs, the FFs in the boundary should always be used.

 

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Don't forget to reply, kudo, and accept as solution.
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Observer kuki
Observer
569 Views
Registered: ‎05-24-2018

Re: set_max_delay for neighborhood Partial Reconfiguration Partitions

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Thanks for the prompt reply @hongh,

 

Locking FFs after initial configuration is the way I was thinking about as well, but unfortunately got too many wires crossing through the neighborhood regions. Locking those FFs will definitely affect the routing, which is already pretty congested.

 

PR is a very nice feature, which has lots of subtle constraints to be considered about. :)

 

Thanks once again for your help

Cheers,
Arsen.

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