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Adventurer
Adventurer
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Registered: ‎11-08-2017

stretch synchronizer -> data transmission for slow-to-fast and fast-to-slow domains -> how to implement?

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Hi All,

 

As for the stretch synchronizer, which supports data transmission for both slow-to-fast and fast-to-slow, how should it be implemented?

 

Thank you!

 

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Mentor
Mentor
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Registered: ‎02-24-2014

you probably want this:  XPM_CDC_HANDSHAKE documented on page 16 of UG953.

 

This macro uses a handshake signaling to transfer an input bus from the source clock domain to the destination clock domain. One example of when this macro should be used is when the data being transferred is not compatible with the XPM_CDC_GRAY macro that uses Gray encoding.

 

For this macro to function correctly, a full handshake - an acknowledgement that the data transfer was received and a resetting of the handshake signals – must be completed before another data transfer is initiated. You can define the number of register stages used in the synchronizers to transfer the handshake signals between the clock domains individually.

 

You can also include internal handshake logic to acknowledge the receipt of data on the destination clock domain. When this feature is enabled, the output (dest_out) must be consumed immediately when the data valid (dest_req) is asserted.

Don't forget to close a thread when possible by accepting a post as a solution.

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Highlighted
Mentor
Mentor
1,349 Views
Registered: ‎02-24-2014

you probably want this:  XPM_CDC_HANDSHAKE documented on page 16 of UG953.

 

This macro uses a handshake signaling to transfer an input bus from the source clock domain to the destination clock domain. One example of when this macro should be used is when the data being transferred is not compatible with the XPM_CDC_GRAY macro that uses Gray encoding.

 

For this macro to function correctly, a full handshake - an acknowledgement that the data transfer was received and a resetting of the handshake signals – must be completed before another data transfer is initiated. You can define the number of register stages used in the synchronizers to transfer the handshake signals between the clock domains individually.

 

You can also include internal handshake logic to acknowledge the receipt of data on the destination clock domain. When this feature is enabled, the output (dest_out) must be consumed immediately when the data valid (dest_req) is asserted.

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post