cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
520 Views
Registered: ‎07-15-2020

trouble making a module into RM because the module appears to be outside the top in hierarchical source viewer

Hi,

We have top module VHDL and use mixed HDL sub-modules under it.  I can't make this sub-module "WORK_MAC" into RM and got the following error message when I "create Partition Definition":
The file /../project_1/...../vlog/WORK_MAC.v that contains the module top WORK_MAC is also used elsewhere in the design in a different context so cannot be made into reconfigurable module.

I did see this sub-module appear outside the top in hierarchy source viewer.  I think it's not being parsed correctly so I have tried manual compile order but it does not help.

In the top module VHDL, we have:

dut_WORK_MAC : WORK_MAC (instantiation)

component WORK_MAC  (declaration)

then we have a WORK_MAC.v

What can I do so that I can make it a RM? I'm using Vivado v2018.3.1 and DFX project flow.

Thanks in advance

Tags (3)
0 Kudos
Reply
8 Replies
Highlighted
Moderator
Moderator
473 Views
Registered: ‎11-04-2010

Hi, @annchen ,

Can the project be synthesized properly without the PR flow?

Can you also try the flow in Vivado 2020.1?

  

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply
Highlighted
Visitor
Visitor
450 Views
Registered: ‎07-15-2020

Thank you so much for replying!
Yes, the project is synthesized properly before I load the project.xpr and convert it to DFX project.  My coworker even tried to re-create the project and still got many sub-modules list outside the top module's hierarchy.  We tried to make the sub-module "WORK_MAC" a black box (use WORK_MAC_BBOX.v) in order to make it a RM (and it worked).  But then the problem becomes how we can put the original WORK_MAC.v back into place.  When I load WORK_MAC.v as a source file for the original WORK_MAC (the 2nd RM), I now have two identical WORK_MAC existing outside the top hierarchy.
We also have Vivado 2019.2 as of now.  How can we get 2020.1?

0 Kudos
Reply
Highlighted
Moderator
Moderator
442 Views
Registered: ‎11-04-2010

Please confirm you add the source files of 2nd RM with PR(DFX)_Wizard.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
pr_wiz.png
0 Kudos
Reply
Highlighted
Visitor
Visitor
435 Views
Registered: ‎07-15-2020

On the Partition Definitions tab, I click on the 2nd RM and right click on the "Edit Reconfiguration module" to add source file WORK_MAC.v.  All the sub-modules of WORK_MAC appear with ? mark in front.  So I have to add the whole directory of Verilog files since they are just too many.

0 Kudos
Reply
Highlighted
Moderator
Moderator
402 Views
Registered: ‎11-04-2010

Yes, all the sub-modules source files of top dynamic cell should be added.

You can also choose to OOC synthesize the RM module in a separate project and export the netlist.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply
Highlighted
Visitor
Visitor
376 Views
Registered: ‎07-15-2020

I even went thru the OOC synth step of the 2nd RM (orginal WORK_MAC.v). Implementation of the 2nd RM has error saying the port or module name does not match.  Anyway these steps each take a while for the graph to be updated/evaluated.  In a second project, I can't reproduce all these steps.  So I'm seeking solutions of not needing to make it a black box in order to make it a RM.

0 Kudos
Reply
Highlighted
Moderator
Moderator
351 Views
Registered: ‎11-04-2010

You can consider to provide a test design if possible.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply
Highlighted
Visitor
Visitor
329 Views
Registered: ‎07-15-2020

Can the tool's script for processing source files into hierarchy handle VHDL top module and mixed VHDL/Verilog sub-modules?

0 Kudos
Reply