07-15-2020 11:53 AM - edited 07-15-2020 11:55 AM
We have top module VHDL and use mixed HDL sub-modules under it. I can't make this sub-module "WORK_MAC" into RM and got the following error message when I "create Partition Definition":
The file /../project_1/...../vlog/WORK_MAC.v that contains the module top WORK_MAC is also used elsewhere in the design in a different context so cannot be made into reconfigurable module.
I did see this sub-module appear outside the top in hierarchy source viewer. I think it's not being parsed correctly so I have tried manual compile order but it does not help.
In the top module VHDL, we have:
dut_WORK_MAC : WORK_MAC (instantiation)
component WORK_MAC (declaration)
then we have a WORK_MAC.v
What can I do so that I can make it a RM? I'm using Vivado v2018.3.1 and DFX project flow.
Thanks in advance
07-16-2020 12:01 AM
Hi, @annchen ,
Can the project be synthesized properly without the PR flow?
Can you also try the flow in Vivado 2020.1?
07-16-2020 08:17 AM
Thank you so much for replying!
Yes, the project is synthesized properly before I load the project.xpr and convert it to DFX project. My coworker even tried to re-create the project and still got many sub-modules list outside the top module's hierarchy. We tried to make the sub-module "WORK_MAC" a black box (use WORK_MAC_BBOX.v) in order to make it a RM (and it worked). But then the problem becomes how we can put the original WORK_MAC.v back into place. When I load WORK_MAC.v as a source file for the original WORK_MAC (the 2nd RM), I now have two identical WORK_MAC existing outside the top hierarchy.
We also have Vivado 2019.2 as of now. How can we get 2020.1?
07-16-2020 08:55 AM
Please confirm you add the source files of 2nd RM with PR(DFX)_Wizard.
07-16-2020 09:30 AM
On the Partition Definitions tab, I click on the 2nd RM and right click on the "Edit Reconfiguration module" to add source file WORK_MAC.v. All the sub-modules of WORK_MAC appear with ? mark in front. So I have to add the whole directory of Verilog files since they are just too many.
07-16-2020 07:30 PM
Yes, all the sub-modules source files of top dynamic cell should be added.
You can also choose to OOC synthesize the RM module in a separate project and export the netlist.
07-17-2020 07:17 AM
I even went thru the OOC synth step of the 2nd RM (orginal WORK_MAC.v). Implementation of the 2nd RM has error saying the port or module name does not match. Anyway these steps each take a while for the graph to be updated/evaluated. In a second project, I can't reproduce all these steps. So I'm seeking solutions of not needing to make it a black box in order to make it a RM.
07-19-2020 07:03 AM
You can consider to provide a test design if possible.