cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
anupkini
Participant
Participant
9,335 Views
Registered: ‎05-16-2012

unable to configure ICAP without help of Microblaze, self written state machine !!

Hi All,

 

I am using Xilinx Suite 13.2 with PlanAhead 13.2 along with Virtex 6 ML605 Evaluation Board

I am tryin to read partial bitstreams from DDR3 and writing them into ICAP_VIRTEX5 entity directly.

 

I have made sure that the data is being read correctly from DDR3 by adding printing them out through UART and Microblaze. So the data is correctly passed. Also i can configure ICAP using Microblaze successfully.

I am unable it without the help of microblaze, using my own state machine.

 

I looked up the XUP document on ICAP Processor Lab (http://www.xilinx.com/university/workshops/partial-reconfiguration-flow/index.htm) that i got from the following link.

 

The timing diagrams match the ones given for write of HWICAP write cycles.

 

I have also included the UNISIM library and UNISIM.vcomponents.all in my vhdl file.

 

I would like to know whether the writes to ICAP_Virtex5 entity need to continues or can have a few clock cycles between every write. Since there are a few idle clock cycles between each data written to ICAP_VIRTEX5 entity.

 

Also, my ICAP_CLK is at 150 Mhz. This works fine with Microblaze so trying without microblaze now.

 

This is a part of the code 

 

if(mem_done = '1') then

 

inc_cnt <= '1';
ICAP_WE <= '0';
ICAP_CE <= '0';
RP_enable <= '0';
RP_reset <= '0';
state <= process_pkt;
Icap_DDR3_E <= '0';


else


inc_cnt <= '0';
ICAP_WE <= '1';
ICAP_CE <= '1';
RP_enable <= '0';
RP_reset <= '0';
state <= process_pkt;
Icap_DDR3_E <= '1';

 

end if;

 

 

 

Thanks,

Anup.

0 Kudos
0 Replies